/**
 * \file    sc8706_reg_defs.h
 * \brief   register definitions for SC8706
 * 
 * \par     Copyright © Unicmicro Co., Ltd. 2022. All rights reserved.
 * \author  ma
 * \date    2022-08-08
 * \version 
 * 
 * \history 
 *  Date        Note
 *  2020-08-08  Original Creation
 * 
 */

#ifndef __SC8706_REG_DEFS_H_
#define __SC8706_REG_DEFS_H_


/** \name  Register access type definition
 * \{ 
 */
#define RO      (0) ///< Read only
#define RC      (1) ///< Read and clear
#define RW      (2) ///< Read and write
#define WC      (3) ///< Write and clear
/** \} */


#define SYS_BAT_BASE_ADDR                                (0xD6)


#define CTRL_OPTION0_L_REG                                (0x00)

/**
Input current gain selection bit
0: 20x (default)
1: 40x
When this bit is to set 0, the IOUTT pin outputs 20X (SNS1P-SNS1N).
*/
#ifndef IOUT_GAIN
#define IOUT_GAIN
#endif
#define CTRL_OPTION0_L_REG_IOUT_GAIN                      (0x04)
#define CTRL_OPTION0_L_REG_IOUT_GAIN_WTH                  (0x01)
#define CTRL_OPTION0_L_REG_IOUT_GAIN_FLDSET               (0x10)
#define CTRL_OPTION0_L_REG_IOUT_GAIN_FLDMSK               (0xEF)
#define CTRL_OPTION0_L_REG_IOUT_GAIN_ACCESS                   RW

/**
Input current gain selection bit
0: 8x
1: 16x (default)
When this bit is set to 1, the IIN pin outputs 16X (SNS2P-SNS2N).
*/
#ifndef IIN_GAIN
#define IIN_GAIN
#endif
#define CTRL_OPTION0_L_REG_IIN_GAIN                      (0x03)
#define CTRL_OPTION0_L_REG_IIN_GAIN_WTH                  (0x01)
#define CTRL_OPTION0_L_REG_IIN_GAIN_FLDSET               (0x08)
#define CTRL_OPTION0_L_REG_IIN_GAIN_FLDMSK               (0xF7)
#define CTRL_OPTION0_L_REG_IIN_GAIN_ACCESS                   RW


#define CTRL_OPTION0_L_REG_ACCESS                             RW
#define CTRL_OPTION0_L_REG_FIELD_COUNT                        (2)


#define CTRL_OPTION0_H_REG                                  (0x01)

/**
Low power mode enable bit
0: performance mode 
1: low power mode (default)
When this bit is set to 1, IC enters low power mode and 
consumes lower quiescent current. The REGN LDO and ADC 
is off, but independent comparator can be enabled by 
corresponding control bit
*/
#ifndef EN_LWPWR
#define EN_LWPWR
#endif
#define CTRL_OPTION0_H_REG_EN_LWPWR                         (0x07)
#define CTRL_OPTION0_H_REG_EN_LWPWR_WTH                     (0x01)
#define CTRL_OPTION0_H_REG_EN_LWPWR_FLDSET                  (0x80)
#define CTRL_OPTION0_H_REG_EN_LWPWR_FLDMSK                  (0x7F)
#define CTRL_OPTION0_H_REG_EN_LWPWR_ACCESS                      RW

/**
Watchdog timer adjust
00: watchdog is disabled
01: 5s
10: 88s
11: 175s (default)
*/
#ifndef WDT_ADJ
#define WDT_ADJ
#endif
#define CTRL_OPTION0_H_REG_WDT_ADJ                         (0x05)
#define CTRL_OPTION0_H_REG_WDT_ADJ_WTH                     (0x02)
#define CTRL_OPTION0_H_REG_WDT_ADJ_FLDSET                  (0x60)
#define CTRL_OPTION0_H_REG_WDT_ADJ_FLDMSK                  (0x9F)
#define CTRL_OPTION0_H_REG_WDT_ADJ_ACCESS                      RW


/**
Enable STAT pin:
0: STAT is enabled (default)
1: STAT is disabled
When this bit is set 1, STAT is internally pulled high to 
indicating DCDC is in normal operation
*/
#ifndef EN_STAT
#define EN_STAT
#endif
#define CTRL_OPTION0_H_REG_EN_STAT                         (0x03)
#define CTRL_OPTION0_H_REG_EN_STAT_WTH                     (0x01)
#define CTRL_OPTION0_H_REG_EN_STAT_FLDSET                  (0x08)
#define CTRL_OPTION0_H_REG_EN_STAT_FLDMSK                  (0xF7)
#define CTRL_OPTION0_H_REG_EN_STAT_ACCESS                      RW

/**
OOA PFM enable bit
0: OOA is disabled
1: OOA is enabled (default)
When this bit is set to 1, OOA out of audio PFM is enabled. IC 
works at least 25kHz PFM mode to avoid audio noise
*/
#ifndef EN_OOA
#define EN_OOA
#endif
#define CTRL_OPTION0_H_REG_EN_OOA                         (0x02)
#define CTRL_OPTION0_H_REG_EN_OOA_WTH                     (0x01)
#define CTRL_OPTION0_H_REG_EN_OOA_FLDSET                  (0x04)
#define CTRL_OPTION0_H_REG_EN_OOA_FLDMSK                  (0xFB)
#define CTRL_OPTION0_H_REG_EN_OOA_ACCESS                      RW

/**
Frequency selection bit
0: 1200kHz
1: 800kHz (default)
*/
#ifndef PWM_FREQ
#define PWM_FREQ
#endif
#define CTRL_OPTION0_H_REG_PWM_FREQ                         (0x01)
#define CTRL_OPTION0_H_REG_PWM_FREQ_WTH                     (0x01)
#define CTRL_OPTION0_H_REG_PWM_FREQ_FLDSET                  (0x02)
#define CTRL_OPTION0_H_REG_PWM_FREQ_FLDMSK                  (0xFD)
#define CTRL_OPTION0_H_REG_PWM_FREQ_ACCESS                      RW

#define CTRL_OPTION0_H_REG_ACCESS                               RW
#define CTRL_OPTION0_H_REG_FIELD_COUNT                          (5)

/**
Output voltage ranges from 3000mV to 20800mV, with 8mV resolution. Any Output voltage command which is not among
3000mV to 20800mV is ignored.
Output DAC offset is decided by Reg0x34<2> bit.
If low Output voltage range bit Reg0x34<2>=1, the offset is 0V, the Output voltage ranges from 3V to 19.52V.
If low Output voltage range bit Reg0x34<2>=0, the offset is 1.28V, the Output voltage ranges from 4.28V to 20.8V.

*/
#define VOUT_SET_1_REG                                        (0x07)

#ifndef VOUTREF_H_SET
#define VOUTREF_H_SET
#endif
#define VOUT_SET_1_REG_VOUTREF_H_SET                         (0x00)
#define VOUT_SET_1_REG_VOUTREF_H_SET_WTH                     (0x06)
#define VOUT_SET_1_REG_VOUTREF_H_SET_FLDSET                  (0x3F)
#define VOUT_SET_1_REG_VOUTREF_H_SET_FLDMSK                  (0xC0)
#define VOUT_SET_1_REG_VOUTREF_H_SET_ACCESS                     RW

#define VOUT_SET_1_REG_ACCESS                                   RW
#define VOUT_SET_1_REG_FIELD_COUNT                              (1)



#define VOUT_SET_0_REG                                        (0x06)

#ifndef VOUTREF_L_SET
#define VOUTREF_L_SET
#endif
#define VOUT_SET_0_REG_VOUTREF_L_SET                        (0x02)
#define VOUT_SET_0_REG_VOUTREF_L_SET_WTH                    (0x06)
#define VOUT_SET_0_REG_VOUTREF_L_SET_FLDSET                 (0xFC)
#define VOUT_SET_0_REG_VOUTREF_L_SET_FLDMSK                 (0x03)
#define VOUT_SET_0_REG_VOUTREF_L_SET_ACCESS                     RW

#define VOUT_SET_0_REG_ACCESS                                   RW
#define VOUT_SET_0_REG_FIELD_COUNT                              (1)



#define IOUT_SET_1_REG                                      (0x09)

/**
Output current ranges from 50mA to 6400mA, with 50mA resolution.

*/
#ifndef IOUTREF_H_SET
#define IOUTREF_H_SET
#endif
#define IOUT_SET_1_REG_IOUTREF_H_SET                        (0x00)
#define IOUT_SET_1_REG_IOUTREF_H_SET_WTH                    (0x07)
#define IOUT_SET_1_REG_IOUTREF_H_SET_FLDSET                 (0x7F)
#define IOUT_SET_1_REG_IOUTREF_H_SET_FLDMSK                 (0x80)
#define IOUT_SET_1_REG_IOUTREF_H_SET_ACCESS                     RW

#define IOUT_SET_1_REG_ACCESS                                   RW
#define IOUT_SET_1_REG_FIELD_COUNT                              (2)


#define FAULTS_STATUS_REG                                   (0x20)

/**
0: no VINOC fault
1: VINOC fault occurs 
If fault is disappeared, this bit is reset to 0 after it is read.

*/
#ifndef Fault_VINOC
#define Fault_VINOC
#endif
#define FAULTS_STATUS_REG_Fault_VINOC                       (0x06)
#define FAULTS_STATUS_REG_Fault_VINOC_WTH                   (0x01)
#define FAULTS_STATUS_REG_Fault_VINOC_FLDSET                (0x40)
#define FAULTS_STATUS_REG_Fault_VINOC_FLDMSK                (0xBF)
#define FAULTS_STATUS_REG_Fault_VINOC_ACCESS                    RW



#ifndef Fault_OUT_OVP
#define Fault_OUT_OVP
#endif
#define FAULTS_STATUS_REG_Fault_OUT_OVP                       (0x01)
#define FAULTS_STATUS_REG_Fault_OUT_OVP_WTH                   (0x01)
#define FAULTS_STATUS_REG_Fault_OUT_OVP_FLDSET                (0x02)
#define FAULTS_STATUS_REG_Fault_OUT_OVP_FLDMSK                (0xFD)
#define FAULTS_STATUS_REG_Fault_OUT_OVP_ACCESS                    RW

#ifndef Fault_OUT_UVP
#define Fault_OUT_UVP
#endif
#define FAULTS_STATUS_REG_Fault_OUT_UVP                         (0x00)
#define FAULTS_STATUS_REG_Fault_OUT_UVP_WTH                     (0x01)
#define FAULTS_STATUS_REG_Fault_OUT_UVP_FLDSET                  (0x01)
#define FAULTS_STATUS_REG_Fault_OUT_UVP_FLDMSK                  (0xFE)
#define FAULTS_STATUS_REG_Fault_OUT_UVP_ACCESS                      RW



#define FAULTS_STATUS_REG_ACCESS                                    RW
#define FAULTS_STATUS_REG_FIELD_COUNT                               (3)





#define CHARGE_STATUS_REG                                         (0x21)


#ifndef DCDC_STAT
#define DCDC_STAT
#endif
#define CHARGE_STATUS_REG_DCDC_STAT                                 (0x00)
#define CHARGE_STATUS_REG_DCDC_STAT_WTH                             (0x01)
#define CHARGE_STATUS_REG_DCDC_STAT_FLDSET                          (0x01)
#define CHARGE_STATUS_REG_DCDC_STAT_FLDMSK                          (0xFE)
#define CHARGE_STATUS_REG_DCDC_STAT_ACCESS                              RW

#define CHARGE_STATUS_REG_ACCESS                                        RW
#define CHARGE_STATUS_REG_FIELD_COUNT                                   (1)


#define ADC_VOUT_REG                                                (0x27)


/**
8-bit Digital output of output voltage
LSB 64mV
Offset: 3.2V
Full Range: 19.52V
*/
#ifndef ADC_VOUT
#define ADC_VOUT
#endif
#define ADC_VOUT_REG_ADC_VOUT                                       (0x00)
#define ADC_VOUT_REG_ADC_VOUT_WTH                                   (0x08)
#define ADC_VOUT_REG_ADC_VOUT_FLDSET                                (0xFF)
#define ADC_VOUT_REG_ADC_VOUT_FLDMSK                                (0x00)
#define ADC_VOUT_REG_ADC_VOUT_ACCESS                                    RO

#define ADC_VOUT_REG_ACCESS                                            RO
#define ADC_VOUT_REG_FIELD_COUNT                                       (1)

#define ADC_IIN_REG                                                 (0x28)

/**
8-bit Digital output of input current IIN 
LSB 256mA
Offset: 0mA
Full Range: 32.512A
*/
#ifndef ADC_IIN
#define ADC_IIN
#endif
#define ADC_IIN_REG_ADC_IIN                                         (0x00)
#define ADC_IIN_REG_ADC_IIN_WTH                                     (0x08)
#define ADC_IIN_REG_ADC_IIN_FLDSET                                  (0xFF)
#define ADC_IIN_REG_ADC_IIN_FLDMSK                                  (0x00)
#define ADC_IIN_REG_ADC_IIN_ACCESS                                      RO



#define ADC_IIN_REG_ACCESS                                              RO
#define ADC_IIN_REG_FIELD_COUNT                                         (1)

#define ADC_IOUT_REG                                                 (0x2B)

/**
8-bit Digital output of output current IOUT
LSB 50mA
Offset: 0mA
Full Range: 6.35A
*/
#ifndef ADC_IOUT
#define ADC_IOUT
#endif
#define ADC_IOUT_REG_ADC_IOUT                                         (0x00)
#define ADC_IOUT_REG_ADC_IOUT_WTH                                     (0x08)
#define ADC_IOUT_REG_ADC_IOUT_FLDSET                                  (0xFF)
#define ADC_IOUT_REG_ADC_IOUT_FLDMSK                                  (0x00)
#define ADC_IOUT_REG_ADC_IOUT_ACCESS                                      RO



#define ADC_IOUT_REG_ACCESS                                              RO
#define ADC_IOUT_REG_FIELD_COUNT                                         (1)


#define ADC_VIN_REG                                                 (0x2C)

/**
8-bit Digital output of input voltage VIN
LSB 64mV
Offset: 2.88V
Full Range: 19.2V
*/
#ifndef ADC_VIN
#define ADC_VIN
#endif
#define ADC_VIN_REG_ADC_VIN                                         (0x00)
#define ADC_VIN_REG_ADC_VIN_WTH                                     (0x08)
#define ADC_VIN_REG_ADC_VIN_FLDSET                                  (0xFF)
#define ADC_VIN_REG_ADC_VIN_FLDMSK                                  (0x00)
#define ADC_VIN_REG_ADC_VIN_ACCESS                                      RO



#define ADC_VIN_REG_ACCESS                                              RO
#define ADC_VIN_REG_FIELD_COUNT                                         (1)



#define CTRL_OPTION1_0_REG                                   (0x30)

/**
Vin Discharger enable bit
0: disable (default)
1: enable
When this bit is set to 1, a 30mA discharging current is pulled 
down from SNS1P pin, after 120ms, the discharging current is 
stopped and this bit is reset to 0
*/
#ifndef VIN_DISC_EN
#define VIN_DISC_EN
#endif
#define CTRL_OPTION1_0_REG_VIN_DISC_EN                            (0x01)
#define CTRL_OPTION1_0_REG_VIN_DISC_EN_WTH                        (0x01)
#define CTRL_OPTION1_0_REG_VIN_DISC_EN_FLDSET                     (0x02)
#define CTRL_OPTION1_0_REG_VIN_DISC_EN_FLDMSK                     (0xFD)
#define CTRL_OPTION1_0_REG_VIN_DISC_EN_ACCESS                     RW


#define CTRL_OPTION1_0_REG_ACCESS                            RW
#define CTRL_OPTION1_0_REG_FIELD_COUNT                       (1)


#define CTRL_OPTION1_1_REG                                   (0x31)

/**
Input current monitor IBAT output enable 
0: disable (default)
1: enable
*/
#ifndef EN_IIN
#define EN_IIN
#endif
#define CTRL_OPTION1_1_REG_EN_IIN                          (0x07)
#define CTRL_OPTION1_1_REG_EN_IIN_WTH                      (0x01)
#define CTRL_OPTION1_1_REG_EN_IIN_FLDSET                   (0x80)
#define CTRL_OPTION1_1_REG_EN_IIN_FLDMSK                   (0x7F)
#define CTRL_OPTION1_1_REG_EN_IIN_ACCESS                   RW

/**
Output current sense resistor
0: 10mΩ (default)
1: 5mΩ
*/
#ifndef RSNS_RS2
#define RSNS_RS2
#endif
#define CTRL_OPTION1_1_REG_RSNS_RS2                          (0x03)
#define CTRL_OPTION1_1_REG_RSNS_RS2_WTH                      (0x01)
#define CTRL_OPTION1_1_REG_RSNS_RS2_FLDSET                   (0x08)
#define CTRL_OPTION1_1_REG_RSNS_RS2_FLDMSK                   (0xF7)
#define CTRL_OPTION1_1_REG_RSNS_RS2_ACCESS                   RW


/**
INput current sense resistor
0: 10mΩ (default)
1: 5mΩ
*/
#ifndef RSNS_RS1
#define RSNS_RS1
#endif
#define CTRL_OPTION1_1_REG_RSNS_RS1                          (0x02)
#define CTRL_OPTION1_1_REG_RSNS_RS1_WTH                      (0x01)
#define CTRL_OPTION1_1_REG_RSNS_RS1_FLDSET                   (0x04)
#define CTRL_OPTION1_1_REG_RSNS_RS1_FLDMSK                   (0xFB)
#define CTRL_OPTION1_1_REG_RSNS_RS1_ACCESS                   RW
#define CTRL_OPTION1_1_REG_ACCESS                            RW
#define CTRL_OPTION1_1_REG_FIELD_COUNT                       (5)


#define CTRL_OPTION2_REG                                   (0x32)

/**
Q2_OCP threshold
0: 210mV
1: 150mV (default)
*/
#ifndef Q2_OCP_VTH
#define Q2_OCP_VTH
#endif
#define CTRL_OPTION2_REG_Q2_OCP_VTH                          (0x05)
#define CTRL_OPTION2_REG_Q2_OCP_VTH_WTH                      (0x01)
#define CTRL_OPTION2_REG_Q2_OCP_VTH_FLDSET                   (0x20)
#define CTRL_OPTION2_REG_Q2_OCP_VTH_FLDMSK                   (0xDF)
#define CTRL_OPTION2_REG_Q2_OCP_VTH_ACCESS                   RW

/**
0: disable VINOC
1: enable VINOC (default)
*/
#ifndef EN_VINOC
#define EN_VINOC
#endif
#define CTRL_OPTION2_REG_EN_VINOC                          (0x01)
#define CTRL_OPTION2_REG_EN_VINOC_WTH                      (0x01)
#define CTRL_OPTION2_REG_EN_VINOC_FLDSET                   (0x02)
#define CTRL_OPTION2_REG_EN_VINOC_FLDMSK                   (0xFD)
#define CTRL_OPTION2_REG_EN_VINOC_ACCESS                   RW

/**
VINOC threshold
0: 133%*IIN_VTH
1: 200%* IIN_VTH (default)
*/
#ifndef VINOC_VTH
#define VINOC_VTH
#endif
#define CTRL_OPTION2_REG_VINOC_VTH                          (0x00)
#define CTRL_OPTION2_REG_VINOC_VTH_WTH                      (0x01)
#define CTRL_OPTION2_REG_VINOC_VTH_FLDSET                   (0x01)
#define CTRL_OPTION2_REG_VINOC_VTH_FLDMSK                   (0xFE)
#define CTRL_OPTION2_REG_VINOC_VTH_ACCESS                   RW


#define CTRL_OPTION2_REG_ACCESS                            RW
#define CTRL_OPTION2_REG_FIELD_COUNT                       (3)


#define CTRL_OPTION3_0_REG                               (0x34)

/**
Inductor average current clamp setting:
00: 6A
01: 10A
10: 15A (default)
11: disable
*/
#ifndef IL_AVG
#define IL_AVG
#endif
#define CTRL_OPTION3_0_REG_IL_AVG                 (0x03)
#define CTRL_OPTION3_0_REG_IL_AVG_WTH             (0x02)
#define CTRL_OPTION3_0_REG_IL_AVG_FLDSET          (0x18)
#define CTRL_OPTION3_0_REG_IL_AVG_FLDMSK          (0xE7)
#define CTRL_OPTION3_0_REG_IL_AVG_ACCESS          RW

/**
Output offset setting
0: 4.28V, output voltage ranges from 4.28V-20.8V(default)
1: 3V, output voltage ranges from 3V-19.52V
*/
#ifndef Output_RANGE_LOW
#define Output_RANGE_LOW
#endif
#define CTRL_OPTION3_0_REG_Output_RANGE_LOW                 (0x02)
#define CTRL_OPTION3_0_REG_Output_RANGE_LOW_WTH             (0x01)
#define CTRL_OPTION3_0_REG_Output_RANGE_LOW_FLDSET          (0x04)
#define CTRL_OPTION3_0_REG_Output_RANGE_LOW_FLDMSK          (0xFB)
#define CTRL_OPTION3_0_REG_Output_RANGE_LOW_ACCESS          RW


#define CTRL_OPTION3_0_REG_ACCESS                        RW
#define CTRL_OPTION3_0_REG_FIELD_COUNT                   (2)


#define CTRL_OPTION3_1_REG                              (0x35)

/**
Reset register
0: idle (default)
1: reset all register
This bit goes back to 0 after register reset.

*/
#ifndef RESET_REG
#define RESET_REG
#endif
#define CTRL_OPTION3_1_REG_RESET_REG               (0x06)
#define CTRL_OPTION3_1_REG_RESET_REG_WTH           (0x01)
#define CTRL_OPTION3_1_REG_RESET_REG_FLDSET        (0x40)
#define CTRL_OPTION3_1_REG_RESET_REG_FLDMSK        (0xBF)
#define CTRL_OPTION3_1_REG_RESET_REG_ACCESS        RW

/**
DCDC control bit
0: disable (default)
1: enable
*/
#ifndef EN_DCDC
#define EN_DCDC
#endif
#define CTRL_OPTION3_1_REG_EN_DCDC               (0x04)
#define CTRL_OPTION3_1_REG_EN_DCDC_WTH           (0x01)
#define CTRL_OPTION3_1_REG_EN_DCDC_FLDSET        (0x10)
#define CTRL_OPTION3_1_REG_EN_DCDC_FLDMSK        (0xEF)
#define CTRL_OPTION3_1_REG_EN_DCDC_ACCESS        RW


#define CTRL_OPTION3_1_REG_ACCESS                       RW
#define CTRL_OPTION3_1_REG_FIELD_COUNT                  (2)


#define IIN_VTH_REG                               (0x39)

/**
IIN threshold 
000001-111111: 0-32256mA, step 512mA. 
100000: 16384 (default) 
There is 128mA offset
*/
#ifndef IIN_VTH
#define IIN_VTH
#endif
#define IIN_VTH_REG_IIN_VTH                    (0x02)
#define IIN_VTH_REG_IIN_VTH_WTH                (0x06)
#define IIN_VTH_REG_IIN_VTH_FLDSET             (0xFC)
#define IIN_VTH_REG_IIN_VTH_FLDMSK             (0x03)
#define IIN_VTH_REG_IIN_VTH_ACCESS              RW

#define IIN_VTH_REG_ACCESS                        RW
#define IIN_VTH_REG_FIELD_COUNT                   (1)


#define ADC_OPTION_0_REG                              (0x3A)

/**
0: disable (default)
1: enable
*/
#ifndef EN_ADC_VOUT
#define EN_ADC_VOUT
#endif
#define ADC_OPTION_0_REG_EN_ADC_VOUT              (0x06)
#define ADC_OPTION_0_REG_EN_ADC_VOUT_WTH          (0x01)
#define ADC_OPTION_0_REG_EN_ADC_VOUT_FLDSET       (0x40)
#define ADC_OPTION_0_REG_EN_ADC_VOUT_FLDMSK       (0xBF)
#define ADC_OPTION_0_REG_EN_ADC_VOUT_ACCESS       RW



/**
0: disable (default)
1: enable
*/
#ifndef EN_ADC_IOUT
#define EN_ADC_IOUT
#endif
#define ADC_OPTION_0_REG_EN_ADC_IOUT              (0x04)
#define ADC_OPTION_0_REG_EN_ADC_IOUT_WTH          (0x01)
#define ADC_OPTION_0_REG_EN_ADC_IOUT_FLDSET       (0x10)
#define ADC_OPTION_0_REG_EN_ADC_IOUT_FLDMSK       (0xEF)
#define ADC_OPTION_0_REG_EN_ADC_IOUT_ACCESS       RW

/**
0: disable (default)
1: enable
*/
#ifndef EN_ADC_IIN
#define EN_ADC_IIN
#endif
#define ADC_OPTION_0_REG_EN_ADC_IIN              (0x03)
#define ADC_OPTION_0_REG_EN_ADC_IIN_WTH          (0x01)
#define ADC_OPTION_0_REG_EN_ADC_IIN_FLDSET       (0x08)
#define ADC_OPTION_0_REG_EN_ADC_IIN_FLDMSK       (0xF7)
#define ADC_OPTION_0_REG_EN_ADC_IIN_ACCESS       RW

/**
0: disable (default)
1: enable
*/
#ifndef EN_ADC_VIN
#define EN_ADC_VIN
#endif
#define ADC_OPTION_0_REG_EN_ADC_VIN              (0x00)
#define ADC_OPTION_0_REG_EN_ADC_VIN_WTH          (0x01)
#define ADC_OPTION_0_REG_EN_ADC_VIN_FLDSET       (0x01)
#define ADC_OPTION_0_REG_EN_ADC_VIN_FLDMSK       (0xFE)
#define ADC_OPTION_0_REG_EN_ADC_VIN_ACCESS       RW

#define ADC_OPTION_0_REG_ACCESS                       RW
#define ADC_OPTION_0_REG_FIELD_COUNT                  (4)


#define ADC_OPTION_1_REG                                  (0x3B)

/**
ADC conversion control
0: one shot mode
1: continuous mode every 1s
*/
#ifndef ADC_CONV
#define ADC_CONV
#endif
#define ADC_OPTION_1_REG_ADC_CONV                       (0x07)
#define ADC_OPTION_1_REG_ADC_CONV_WTH                   (0x01)
#define ADC_OPTION_1_REG_ADC_CONV_FLDSET                (0x80)
#define ADC_OPTION_1_REG_ADC_CONV_FLDMSK                (0x7F)
#define ADC_OPTION_1_REG_ADC_CONV_ACCESS                RW

/**
ADC conversion start
0: no ADC conversion
1: Start ADC conversion and goes back to 0 after one-shot 
conversion is finished
*/
#ifndef ADC_START
#define ADC_START
#endif
#define ADC_OPTION_1_REG_ADC_START                       (0x06)
#define ADC_OPTION_1_REG_ADC_START_WTH                   (0x01)
#define ADC_OPTION_1_REG_ADC_START_FLDSET                (0x40)
#define ADC_OPTION_1_REG_ADC_START_FLDMSK                (0xBF)
#define ADC_OPTION_1_REG_ADC_START_ACCESS                RW


#define ADC_OPTION_1_REG_ACCESS                           RW
#define ADC_OPTION_1_REG_FIELD_COUNT                      (1)

#endif /* #ifndef __SC8706_REG_DEFS_H_ */

