/**
 * \file    reg_def_flash.h
 * \brief   Register definition file
 * 
 * \par     Copyright (c) 2019 UWE Technologies Corp., Ltd. All Rights Reserved.
 * \author  James
 * \date    2019-04-26
 * \version 
 * 
 * \history 
 *  Date        Note
 *  2019-04-26  Original Creation
 * 
 */

#ifndef __REG_DEF_FLASH_H_
#define __REG_DEF_FLASH_H_



#define FLASH_CTRL_REG                                  (0x40000D00)

/**
T_SHSL, RW, reset value(0x1)
Flash AC Electrical characteristics tSHSL. In unit of spi_clk cycles.
*/
#ifndef T_SHSL
#define T_SHSL
#endif
#define FLASH_CTRL_REG_T_SHSL                           (0x08)
#define FLASH_CTRL_REG_T_SHSL_WTH                       (0x04)
#define FLASH_CTRL_REG_T_SHSL_FLDSET                    (0x00000F00)
#define FLASH_CTRL_REG_T_SHSL_FLDMSK                    (0xFFFFF0FF)

/**
FLASH_DM_W32B_MODE, RW, reset value(0x0)
1: Enable the mode for  DMA write 32 Bytes to FLASH together.
*/
#ifndef FLASH_DM_W32B_MODE
#define FLASH_DM_W32B_MODE
#endif
#define FLASH_CTRL_REG_FLASH_DM_W32B_MODE               (0x03)
#define FLASH_CTRL_REG_FLASH_DM_W32B_MODE_WTH           (0x01)
#define FLASH_CTRL_REG_FLASH_DM_W32B_MODE_FLDSET        (0x00000008)
#define FLASH_CTRL_REG_FLASH_DM_W32B_MODE_FLDMSK        (0xFFFFFFF7)

/**
FLASH_PRG_ENA, RW, reset value(0x1)
1'b1: UART program FLASH is enabled.
*/
#ifndef FLASH_PRG_ENA
#define FLASH_PRG_ENA
#endif
#define FLASH_CTRL_REG_FLASH_PRG_ENA                    (0x02)
#define FLASH_CTRL_REG_FLASH_PRG_ENA_WTH                (0x01)
#define FLASH_CTRL_REG_FLASH_PRG_ENA_FLDSET             (0x00000004)
#define FLASH_CTRL_REG_FLASH_PRG_ENA_FLDMSK             (0xFFFFFFFB)

/**
SECURITY_REG_ACC, RW, reset value(0x0)
1'b1 : Flash security register access is selected, 1'b0 : Flash main region is selected.
*/
#ifndef SECURITY_REG_ACC
#define SECURITY_REG_ACC
#endif
#define FLASH_CTRL_REG_SECURITY_REG_ACC                 (0x01)
#define FLASH_CTRL_REG_SECURITY_REG_ACC_WTH             (0x01)
#define FLASH_CTRL_REG_SECURITY_REG_ACC_FLDSET          (0x00000002)
#define FLASH_CTRL_REG_SECURITY_REG_ACC_FLDMSK          (0xFFFFFFFD)

/**
DAHB_WRITE_FLASH_ENA, RW, reset value(0x0)
1'b1 : MCU D-AHB write access  flash is enabled, 1'b0: D-AHB write access flash is diabled.
*/
#ifndef DAHB_WRITE_FLASH_ENA
#define DAHB_WRITE_FLASH_ENA
#endif
#define FLASH_CTRL_REG_DAHB_WRITE_FLASH_ENA             (0x00)
#define FLASH_CTRL_REG_DAHB_WRITE_FLASH_ENA_WTH         (0x01)
#define FLASH_CTRL_REG_DAHB_WRITE_FLASH_ENA_FLDSET      (0x00000001)
#define FLASH_CTRL_REG_DAHB_WRITE_FLASH_ENA_FLDMSK      (0xFFFFFFFE)



#endif /* #ifndef __REG_DEF_FLASH_H_ */

