/**
 * \file    reg_def_pd.h
 * \brief   Register definition file
 * 
 * \par     Copyright (c) 2019 UWE Technologies Corp., Ltd. All Rights Reserved.
 * \author  James
 * \date    2019-04-25
 * \version 
 * 
 * \history 
 *  Date        Note
 *  2019-04-25  Original Creation
 * 
 */

#ifndef __REG_DEF_PD_H_
#define __REG_DEF_PD_H_



#define DPM_REG_1                                       (0x40000004)

/**
CC2_ISET, RW, reset value(0x0)
CC2 current source setting
*/
#ifndef CC2_ISET
#define CC2_ISET
#endif
#define DPM_REG_1_CC2_ISET                              (0x11)
#define DPM_REG_1_CC2_ISET_WTH                          (0x02)
#define DPM_REG_1_CC2_ISET_FLDSET                       (0x00060000)
#define DPM_REG_1_CC2_ISET_FLDMSK                       (0xFFF9FFFF)

/**
RX_FILTER_SEL, RW, reset value(0x0)
CC IO receive signal glitch filter selection. 
2'b00 : filter glitches less than 2 clock width, 
2'b01 : filter glitches less than 3 clock width,
2'b10 : filter glitches less than 4 clock width,
2'b11 : no filter.
*/
#ifndef RX_FILTER_SEL
#define RX_FILTER_SEL
#endif
#define DPM_REG_1_RX_FILTER_SEL                         (0x0F)
#define DPM_REG_1_RX_FILTER_SEL_WTH                     (0x02)
#define DPM_REG_1_RX_FILTER_SEL_FLDSET                  (0x00018000)
#define DPM_REG_1_RX_FILTER_SEL_FLDMSK                  (0xFFFE7FFF)

/**
BIST_MODE, RW, reset value(0x0)
BIST carrier mode 2 enable, set by SW, clear by HW automatically
*/
#ifndef BIST_MODE
#define BIST_MODE
#endif
#define DPM_REG_1_BIST_MODE                             (0x0E)
#define DPM_REG_1_BIST_MODE_WTH                         (0x01)
#define DPM_REG_1_BIST_MODE_FLDSET                      (0x00004000)
#define DPM_REG_1_BIST_MODE_FLDMSK                      (0xFFFFBFFF)

/**
VBUS_DISCH, RW, reset value(0x0)
1'b1 : discharge VBUS, 1'b0 : not discharge
*/
#ifndef VBUS_DISCH
#define VBUS_DISCH
#endif
#define DPM_REG_1_VBUS_DISCH                            (0x0D)
#define DPM_REG_1_VBUS_DISCH_WTH                        (0x01)
#define DPM_REG_1_VBUS_DISCH_FLDSET                     (0x00002000)
#define DPM_REG_1_VBUS_DISCH_FLDMSK                     (0xFFFFDFFF)

/**
HALF_BIT_SEL, RW, reset value(0x3)
3'b000 : half bit toggle identify tolerant 1/16 duty cycle. 
3'b001 : half bit toggle identify tolerant 2/16 duty cycle.
3'b010 : half bit toggle identify tolerant 3/16 duty cycle.
3'b011 : half bit toggle identify tolerant 4/16 duty cycle.
3'b100 : half bit toggle identify tolerant 5/16 duty cycle.
Others : half bit toggle identify tolerant 6/16 duty cycle.
*/
#ifndef HALF_BIT_SEL
#define HALF_BIT_SEL
#endif
#define DPM_REG_1_HALF_BIT_SEL                          (0x0A)
#define DPM_REG_1_HALF_BIT_SEL_WTH                      (0x03)
#define DPM_REG_1_HALF_BIT_SEL_FLDSET                   (0x00001C00)
#define DPM_REG_1_HALF_BIT_SEL_FLDMSK                   (0xFFFFE3FF)

/**
ORIENT_SELECT, RW, reset value(0x0)
0: CC1; 1: CC2
*/
#ifndef ORIENT_SELECT
#define ORIENT_SELECT
#endif
#define DPM_REG_1_ORIENT_SELECT                         (0x09)
#define DPM_REG_1_ORIENT_SELECT_WTH                     (0x01)
#define DPM_REG_1_ORIENT_SELECT_FLDSET                  (0x00000200)
#define DPM_REG_1_ORIENT_SELECT_FLDMSK                  (0xFFFFFDFF)

/**
CAB_DETECT_DONE, RW, reset value(0x0)
1: Cable Detection Done
0: Cable Detection NOT Done
*/
#ifndef CAB_DETECT_DONE
#define CAB_DETECT_DONE
#endif
#define DPM_REG_1_CAB_DETECT_DONE                       (0x08)
#define DPM_REG_1_CAB_DETECT_DONE_WTH                   (0x01)
#define DPM_REG_1_CAB_DETECT_DONE_FLDSET                (0x00000100)
#define DPM_REG_1_CAB_DETECT_DONE_FLDMSK                (0xFFFFFEFF)

/**
CAPTRUE_MODE, RW, reset value(0x0)
1: Capture Mode. 0: Normal mode
*/
#ifndef CAPTRUE_MODE
#define CAPTRUE_MODE
#endif
#define DPM_REG_1_CAPTRUE_MODE                          (0x07)
#define DPM_REG_1_CAPTRUE_MODE_WTH                      (0x01)
#define DPM_REG_1_CAPTRUE_MODE_FLDSET                   (0x00000080)
#define DPM_REG_1_CAPTRUE_MODE_FLDMSK                   (0xFFFFFF7F)

/**
CC2_ROUGH_RD_EN, RW, reset value(0x1)
CC2 rough Rd enable, active high
*/
#ifndef CC2_ROUGH_RD_EN
#define CC2_ROUGH_RD_EN
#endif
#define DPM_REG_1_CC2_ROUGH_RD_EN                       (0x06)
#define DPM_REG_1_CC2_ROUGH_RD_EN_WTH                   (0x01)
#define DPM_REG_1_CC2_ROUGH_RD_EN_FLDSET                (0x00000040)
#define DPM_REG_1_CC2_ROUGH_RD_EN_FLDMSK                (0xFFFFFFBF)

/**
CC1_ROUGH_RD_EN, RW, reset value(0x1)
CC1 rough Rd enable, active high
*/
#ifndef CC1_ROUGH_RD_EN
#define CC1_ROUGH_RD_EN
#endif
#define DPM_REG_1_CC1_ROUGH_RD_EN                       (0x05)
#define DPM_REG_1_CC1_ROUGH_RD_EN_WTH                   (0x01)
#define DPM_REG_1_CC1_ROUGH_RD_EN_FLDSET                (0x00000020)
#define DPM_REG_1_CC1_ROUGH_RD_EN_FLDMSK                (0xFFFFFFDF)

/**
CC1_ISET, RW, reset value(0x0)
in ASIC mode, these two bits set the cc1 current source, in FPGA mode, these two bits enables CC1 and CC2's Rp pull-up resistor individually. 
*/
#ifndef CC1_ISET
#define CC1_ISET
#endif
#define DPM_REG_1_CC1_ISET                              (0x02)
#define DPM_REG_1_CC1_ISET_WTH                          (0x02)
#define DPM_REG_1_CC1_ISET_FLDSET                       (0x0000000C)
#define DPM_REG_1_CC1_ISET_FLDMSK                       (0xFFFFFFF3)

/**
CC2_RD_EN, RW, reset value(0x0)
1'b1: Enable Rd on CC2, default value when ASIC is 1'b0, when FPGA is 1'b1
*/
#ifndef CC2_RD_EN
#define CC2_RD_EN
#endif
#define DPM_REG_1_CC2_RD_EN                             (0x01)
#define DPM_REG_1_CC2_RD_EN_WTH                         (0x01)
#define DPM_REG_1_CC2_RD_EN_FLDSET                      (0x00000002)
#define DPM_REG_1_CC2_RD_EN_FLDMSK                      (0xFFFFFFFD)

/**
CC1_RD_EN, RW, reset value(0x0)
1'b1: Enable Rd on CC1, default value when ASIC is 1'b0, when FPGA is 1'b1
*/
#ifndef CC1_RD_EN
#define CC1_RD_EN
#endif
#define DPM_REG_1_CC1_RD_EN                             (0x00)
#define DPM_REG_1_CC1_RD_EN_WTH                         (0x01)
#define DPM_REG_1_CC1_RD_EN_FLDSET                      (0x00000001)
#define DPM_REG_1_CC1_RD_EN_FLDMSK                      (0xFFFFFFFE)


#define DPM_PRL_REG                                     (0x40000008)

/**
FRS_TX_ENA, RW, reset value(0x0)
FRS signal is transmit when this bit is set to high, SW should set and clear this bit to match the timing of tFRSwapTx (60us ~ 120us).
*/
#ifndef FRS_TX_ENA
#define FRS_TX_ENA
#endif
#define DPM_PRL_REG_FRS_TX_ENA                          (0x15)
#define DPM_PRL_REG_FRS_TX_ENA_WTH                      (0x01)
#define DPM_PRL_REG_FRS_TX_ENA_FLDSET                   (0x00200000)
#define DPM_PRL_REG_FRS_TX_ENA_FLDMSK                   (0xFFDFFFFF)

/**
FRS_ENA, RW, reset value(0x0)
1'b1 : FRS feature is enabled, only when this bit is set 1, the FRS detect and transmit is enabled.
*/
#ifndef FRS_ENA
#define FRS_ENA
#endif
#define DPM_PRL_REG_FRS_ENA                             (0x14)
#define DPM_PRL_REG_FRS_ENA_WTH                         (0x01)
#define DPM_PRL_REG_FRS_ENA_FLDSET                      (0x00100000)
#define DPM_PRL_REG_FRS_ENA_FLDMSK                      (0xFFEFFFFF)

/**
LOCAL_HW_RESET, RW, reset value(0x0)
Local Hardware reset, configured by SW PE state machine, will reset protocol and phy layer, 
This register is also be set when DPM receive SOFT RESET message.
*/
#ifndef LOCAL_HW_RESET
#define LOCAL_HW_RESET
#endif
#define DPM_PRL_REG_LOCAL_HW_RESET                      (0x12)
#define DPM_PRL_REG_LOCAL_HW_RESET_WTH                  (0x01)
#define DPM_PRL_REG_LOCAL_HW_RESET_FLDSET               (0x00040000)
#define DPM_PRL_REG_LOCAL_HW_RESET_FLDMSK               (0xFFFBFFFF)

/**
HRST_REQ_FRM_PLCENG, RW, reset value(0x0)
Hard Reset request from policy engine
*/
#ifndef HRST_REQ_FRM_PLCENG
#define HRST_REQ_FRM_PLCENG
#endif
#define DPM_PRL_REG_HRST_REQ_FRM_PLCENG                 (0x11)
#define DPM_PRL_REG_HRST_REQ_FRM_PLCENG_WTH             (0x01)
#define DPM_PRL_REG_HRST_REQ_FRM_PLCENG_FLDSET          (0x00020000)
#define DPM_PRL_REG_HRST_REQ_FRM_PLCENG_FLDMSK          (0xFFFDFFFF)

/**
CBL_RST_REQ_FRM_PLCENG, RW, reset value(0x0)
Cable Reset request from policy engine
*/
#ifndef CBL_RST_REQ_FRM_PLCENG
#define CBL_RST_REQ_FRM_PLCENG
#endif
#define DPM_PRL_REG_CBL_RST_REQ_FRM_PLCENG              (0x10)
#define DPM_PRL_REG_CBL_RST_REQ_FRM_PLCENG_WTH          (0x01)
#define DPM_PRL_REG_CBL_RST_REQ_FRM_PLCENG_FLDSET       (0x00010000)
#define DPM_PRL_REG_CBL_RST_REQ_FRM_PLCENG_FLDMSK       (0xFFFEFFFF)

/**
RETRY_CNT, RW, reset value(0x0)
TX message retry counter setting.
*/
#ifndef RETRY_CNT
#define RETRY_CNT
#endif
#define DPM_PRL_REG_RETRY_CNT                           (0x0E)
#define DPM_PRL_REG_RETRY_CNT_WTH                       (0x02)
#define DPM_PRL_REG_RETRY_CNT_FLDSET                    (0x0000C000)
#define DPM_PRL_REG_RETRY_CNT_FLDMSK                    (0xFFFF3FFF)

/**
LARGE_EXTENDED_MSG, RW, reset value(0x0)
0: legacy PD2.0 message or PD3.0 extended message bug data size not larger than maximum  legacy message length.
1: PD3.0 extended message and data size larger than maximum  legacy message length.
*/
#ifndef LARGE_EXTENDED_MSG
#define LARGE_EXTENDED_MSG
#endif
#define DPM_PRL_REG_LARGE_EXTENDED_MSG                  (0x0D)
#define DPM_PRL_REG_LARGE_EXTENDED_MSG_WTH              (0x01)
#define DPM_PRL_REG_LARGE_EXTENDED_MSG_FLDSET           (0x00002000)
#define DPM_PRL_REG_LARGE_EXTENDED_MSG_FLDMSK           (0xFFFFDFFF)

/**
CABLE_PLUG, RW, reset value(0x0)
0 : Message originated from Source, Sink or DRP
1 : Message originated from a cable plug
*/
#ifndef CABLE_PLUG
#define CABLE_PLUG
#endif
#define DPM_PRL_REG_CABLE_PLUG                          (0x0C)
#define DPM_PRL_REG_CABLE_PLUG_WTH                      (0x01)
#define DPM_PRL_REG_CABLE_PLUG_FLDSET                   (0x00001000)
#define DPM_PRL_REG_CABLE_PLUG_FLDMSK                   (0xFFFFEFFF)

/**
DATA_ROLE, RW, reset value(0x0)
0 : UFP
1 : DFP
*/
#ifndef DATA_ROLE
#define DATA_ROLE
#endif
#define DPM_PRL_REG_DATA_ROLE                           (0x0B)
#define DPM_PRL_REG_DATA_ROLE_WTH                       (0x01)
#define DPM_PRL_REG_DATA_ROLE_FLDSET                    (0x00000800)
#define DPM_PRL_REG_DATA_ROLE_FLDMSK                    (0xFFFFF7FF)

/**
USB_PD_SPEC_REV, RW, reset value(0x0)
00b : Revision 1.0
01b : Revision 2.0
Others : Reserved
*/
#ifndef USB_PD_SPEC_REV
#define USB_PD_SPEC_REV
#endif
#define DPM_PRL_REG_USB_PD_SPEC_REV                     (0x09)
#define DPM_PRL_REG_USB_PD_SPEC_REV_WTH                 (0x02)
#define DPM_PRL_REG_USB_PD_SPEC_REV_FLDSET              (0x00000600)
#define DPM_PRL_REG_USB_PD_SPEC_REV_FLDMSK              (0xFFFFF9FF)

/**
PWR_ROLE, RW, reset value(0x0)
0 : Sink
1 : Source
*/
#ifndef PWR_ROLE
#define PWR_ROLE
#endif
#define DPM_PRL_REG_PWR_ROLE                            (0x08)
#define DPM_PRL_REG_PWR_ROLE_WTH                        (0x01)
#define DPM_PRL_REG_PWR_ROLE_FLDSET                     (0x00000100)
#define DPM_PRL_REG_PWR_ROLE_FLDMSK                     (0xFFFFFEFF)

/**
ENABLE_CABLE_RESET, RW, reset value(0x0)
0 : TCPC does not detect cable reset signaling (default)
1 : TCPC detect cable reset signaling
*/
#ifndef ENABLE_CABLE_RESET
#define ENABLE_CABLE_RESET
#endif
#define DPM_PRL_REG_ENABLE_CABLE_RESET                  (0x06)
#define DPM_PRL_REG_ENABLE_CABLE_RESET_WTH              (0x01)
#define DPM_PRL_REG_ENABLE_CABLE_RESET_FLDSET           (0x00000040)
#define DPM_PRL_REG_ENABLE_CABLE_RESET_FLDMSK           (0xFFFFFFBF)

/**
ENABLE_HARD_RESET, RW, reset value(0x0)
0 : TCPC does not detect hard reset signaling (default)
1 : TCPC detect hard reset signaling
*/
#ifndef ENABLE_HARD_RESET
#define ENABLE_HARD_RESET
#endif
#define DPM_PRL_REG_ENABLE_HARD_RESET                   (0x05)
#define DPM_PRL_REG_ENABLE_HARD_RESET_WTH               (0x01)
#define DPM_PRL_REG_ENABLE_HARD_RESET_FLDSET            (0x00000020)
#define DPM_PRL_REG_ENABLE_HARD_RESET_FLDMSK            (0xFFFFFFDF)

/**
ENABLE_SOP2_DBG, RW, reset value(0x0)
0 : TCPC does not detect SOP''_DBG message (default)
1 : TCPC detect SOP''_DBG message
*/
#ifndef ENABLE_SOP2_DBG
#define ENABLE_SOP2_DBG
#endif
#define DPM_PRL_REG_ENABLE_SOP2_DBG                     (0x04)
#define DPM_PRL_REG_ENABLE_SOP2_DBG_WTH                 (0x01)
#define DPM_PRL_REG_ENABLE_SOP2_DBG_FLDSET              (0x00000010)
#define DPM_PRL_REG_ENABLE_SOP2_DBG_FLDMSK              (0xFFFFFFEF)

/**
ENABLE_SOP1_DBG, RW, reset value(0x0)
0 : TCPC does not detect SOP'_DBG message (default)
1 : TCPC detect SOP'_DBG message
*/
#ifndef ENABLE_SOP1_DBG
#define ENABLE_SOP1_DBG
#endif
#define DPM_PRL_REG_ENABLE_SOP1_DBG                     (0x03)
#define DPM_PRL_REG_ENABLE_SOP1_DBG_WTH                 (0x01)
#define DPM_PRL_REG_ENABLE_SOP1_DBG_FLDSET              (0x00000008)
#define DPM_PRL_REG_ENABLE_SOP1_DBG_FLDMSK              (0xFFFFFFF7)

/**
ENABLE_SOP2_MSG, RW, reset value(0x0)
0 : TCPC does not detect SOP'' message (default)
1 : TCPC detect SOP'' message
*/
#ifndef ENABLE_SOP2_MSG
#define ENABLE_SOP2_MSG
#endif
#define DPM_PRL_REG_ENABLE_SOP2_MSG                     (0x02)
#define DPM_PRL_REG_ENABLE_SOP2_MSG_WTH                 (0x01)
#define DPM_PRL_REG_ENABLE_SOP2_MSG_FLDSET              (0x00000004)
#define DPM_PRL_REG_ENABLE_SOP2_MSG_FLDMSK              (0xFFFFFFFB)

/**
ENABLE_SOP1_MSG, RW, reset value(0x0)
0 : TCPC does not detect SOP' message (default)
1 : TCPC detect SOP' message
*/
#ifndef ENABLE_SOP1_MSG
#define ENABLE_SOP1_MSG
#endif
#define DPM_PRL_REG_ENABLE_SOP1_MSG                     (0x01)
#define DPM_PRL_REG_ENABLE_SOP1_MSG_WTH                 (0x01)
#define DPM_PRL_REG_ENABLE_SOP1_MSG_FLDSET              (0x00000002)
#define DPM_PRL_REG_ENABLE_SOP1_MSG_FLDMSK              (0xFFFFFFFD)

/**
ENABLE_SOP_MSG, RW, reset value(0x0)
0 : TCPC does not detect SOP message (default)
1 : TCPC detect SOP message
*/
#ifndef ENABLE_SOP_MSG
#define ENABLE_SOP_MSG
#endif
#define DPM_PRL_REG_ENABLE_SOP_MSG                      (0x00)
#define DPM_PRL_REG_ENABLE_SOP_MSG_WTH                  (0x01)
#define DPM_PRL_REG_ENABLE_SOP_MSG_FLDSET               (0x00000001)
#define DPM_PRL_REG_ENABLE_SOP_MSG_FLDMSK               (0xFFFFFFFE)


#define DPM_INT_EN_REG                                  (0x4000000C)

/**
INT_ENA, RW, reset value(0x0)
Global Interrupt Disable/Enable
1: Enable
0: Disable
*/
#ifndef INT_ENA
#define INT_ENA
#endif
#define DPM_INT_EN_REG_INT_ENA                          (0x00)
#define DPM_INT_EN_REG_INT_ENA_WTH                      (0x01)
#define DPM_INT_EN_REG_INT_ENA_FLDSET                   (0x00000001)
#define DPM_INT_EN_REG_INT_ENA_FLDMSK                   (0xFFFFFFFE)


#define DPM_INT_STATUS_REG                              (0x40000010)

/**
FRS_SIG_DETECTED, RC, reset value(0x0)
FRS signal is detected.
*/
#ifndef FRS_SIG_DETECTED
#define FRS_SIG_DETECTED
#endif
#define DPM_INT_STATUS_REG_FRS_SIG_DETECTED             (0x0D)
#define DPM_INT_STATUS_REG_FRS_SIG_DETECTED_WTH         (0x01)
#define DPM_INT_STATUS_REG_FRS_SIG_DETECTED_FLDSET      (0x00002000)
#define DPM_INT_STATUS_REG_FRS_SIG_DETECTED_FLDMSK      (0xFFFFDFFF)

/**
HW_TIMER3_TIMEOUT, RC, reset value(0x0)
*/
#ifndef HW_TIMER3_TIMEOUT
#define HW_TIMER3_TIMEOUT
#endif
#define DPM_INT_STATUS_REG_HW_TIMER3_TIMEOUT            (0x0C)
#define DPM_INT_STATUS_REG_HW_TIMER3_TIMEOUT_WTH        (0x01)
#define DPM_INT_STATUS_REG_HW_TIMER3_TIMEOUT_FLDSET     (0x00001000)
#define DPM_INT_STATUS_REG_HW_TIMER3_TIMEOUT_FLDMSK     (0xFFFFEFFF)

/**
HW_TIMER2_TIMEOUT, RC, reset value(0x0)
*/
#ifndef HW_TIMER2_TIMEOUT
#define HW_TIMER2_TIMEOUT
#endif
#define DPM_INT_STATUS_REG_HW_TIMER2_TIMEOUT            (0x0B)
#define DPM_INT_STATUS_REG_HW_TIMER2_TIMEOUT_WTH        (0x01)
#define DPM_INT_STATUS_REG_HW_TIMER2_TIMEOUT_FLDSET     (0x00000800)
#define DPM_INT_STATUS_REG_HW_TIMER2_TIMEOUT_FLDMSK     (0xFFFFF7FF)

/**
HW_TIMER1_TIMEOUT, RC, reset value(0x0)
*/
#ifndef HW_TIMER1_TIMEOUT
#define HW_TIMER1_TIMEOUT
#endif
#define DPM_INT_STATUS_REG_HW_TIMER1_TIMEOUT            (0x0A)
#define DPM_INT_STATUS_REG_HW_TIMER1_TIMEOUT_WTH        (0x01)
#define DPM_INT_STATUS_REG_HW_TIMER1_TIMEOUT_FLDSET     (0x00000400)
#define DPM_INT_STATUS_REG_HW_TIMER1_TIMEOUT_FLDMSK     (0xFFFFFBFF)

/**
PHY_RXFIFO_CLEAR, RC, reset value(0x0)
PHY Receive FIFO is cleared due to abnomal frame is received, such as CRC error, or no eop
*/
#ifndef PHY_RXFIFO_CLEAR
#define PHY_RXFIFO_CLEAR
#endif
#define DPM_INT_STATUS_REG_PHY_RXFIFO_CLEAR             (0x09)
#define DPM_INT_STATUS_REG_PHY_RXFIFO_CLEAR_WTH         (0x01)
#define DPM_INT_STATUS_REG_PHY_RXFIFO_CLEAR_FLDSET      (0x00000200)
#define DPM_INT_STATUS_REG_PHY_RXFIFO_CLEAR_FLDMSK      (0xFFFFFDFF)

/**
DPM_RX_MSG, RC, reset value(0x0)
When SW got this interrupt do following operation:
Read DMA_BUFF_REG4 to get related information about received message.
*/
#ifndef DPM_RX_MSG
#define DPM_RX_MSG
#endif
#define DPM_INT_STATUS_REG_DPM_RX_MSG                   (0x08)
#define DPM_INT_STATUS_REG_DPM_RX_MSG_WTH               (0x01)
#define DPM_INT_STATUS_REG_DPM_RX_MSG_FLDSET            (0x00000100)
#define DPM_INT_STATUS_REG_DPM_RX_MSG_FLDMSK            (0xFFFFFEFF)

/**
SOP_NOT_DETECTED, RC, reset value(0x0)
cc toggled, but sop kcode is not detected.
*/
#ifndef SOP_NOT_DETECTED
#define SOP_NOT_DETECTED
#endif
#define DPM_INT_STATUS_REG_SOP_NOT_DETECTED             (0x07)
#define DPM_INT_STATUS_REG_SOP_NOT_DETECTED_WTH         (0x01)
#define DPM_INT_STATUS_REG_SOP_NOT_DETECTED_FLDSET      (0x00000080)
#define DPM_INT_STATUS_REG_SOP_NOT_DETECTED_FLDMSK      (0xFFFFFF7F)

/**
FRS_DETECTED, RC, reset value(0x0)
FRS signal is detected. 
*/
#ifndef FRS_DETECTED
#define FRS_DETECTED
#endif
#define DPM_INT_STATUS_REG_FRS_DETECTED                 (0x06)
#define DPM_INT_STATUS_REG_FRS_DETECTED_WTH             (0x01)
#define DPM_INT_STATUS_REG_FRS_DETECTED_FLDSET          (0x00000040)
#define DPM_INT_STATUS_REG_FRS_DETECTED_FLDMSK          (0xFFFFFFBF)

/**
CABLE_RESET_SIG_FRM_PHY, RC, reset value(0x0)
Cable Reset Signal received from PHY
*/
#ifndef CABLE_RESET_SIG_FRM_PHY
#define CABLE_RESET_SIG_FRM_PHY
#endif
#define DPM_INT_STATUS_REG_CABLE_RESET_SIG_FRM_PHY      (0x05)
#define DPM_INT_STATUS_REG_CABLE_RESET_SIG_FRM_PHY_WTH  (0x01)
#define DPM_INT_STATUS_REG_CABLE_RESET_SIG_FRM_PHY_FLDSET (0x00000020)
#define DPM_INT_STATUS_REG_CABLE_RESET_SIG_FRM_PHY_FLDMSK (0xFFFFFFDF)

/**
HARD_RESET_SIG_FRM_PHY, RC, reset value(0x0)
Hard Reset Signal recevied from PHY
*/
#ifndef HARD_RESET_SIG_FRM_PHY
#define HARD_RESET_SIG_FRM_PHY
#endif
#define DPM_INT_STATUS_REG_HARD_RESET_SIG_FRM_PHY       (0x04)
#define DPM_INT_STATUS_REG_HARD_RESET_SIG_FRM_PHY_WTH   (0x01)
#define DPM_INT_STATUS_REG_HARD_RESET_SIG_FRM_PHY_FLDSET (0x00000010)
#define DPM_INT_STATUS_REG_HARD_RESET_SIG_FRM_PHY_FLDMSK (0xFFFFFFEF)

/**
RX_BUFF_FULL, RC, reset value(0x0)
1: RX message buffer is full
*/
#ifndef RX_BUFF_FULL
#define RX_BUFF_FULL
#endif
#define DPM_INT_STATUS_REG_RX_BUFF_FULL                 (0x03)
#define DPM_INT_STATUS_REG_RX_BUFF_FULL_WTH             (0x01)
#define DPM_INT_STATUS_REG_RX_BUFF_FULL_FLDSET          (0x00000008)
#define DPM_INT_STATUS_REG_RX_BUFF_FULL_FLDMSK          (0xFFFFFFF7)

/**
TX_SOP_MSG_SUCCESS, RC, reset value(0x0)
0: cleared;  1: Reset or SOP* message transmission successful. Good CRC received and TX BUFFER registers are empty.
Note: when TX_SOP_MSG_SUCCESS and TX_SOP_MSG_FAILED interrupt are set to 1 both, it indicates the HARD_RST or 
CABLE_HARD_RST signal is sent done by PHY.
*/
#ifndef TX_SOP_MSG_SUCCESS
#define TX_SOP_MSG_SUCCESS
#endif
#define DPM_INT_STATUS_REG_TX_SOP_MSG_SUCCESS           (0x02)
#define DPM_INT_STATUS_REG_TX_SOP_MSG_SUCCESS_WTH       (0x01)
#define DPM_INT_STATUS_REG_TX_SOP_MSG_SUCCESS_FLDSET    (0x00000004)
#define DPM_INT_STATUS_REG_TX_SOP_MSG_SUCCESS_FLDMSK    (0xFFFFFFFB)

/**
TX_SOP_MSG_FAILED, RC, reset value(0x0)
0: cleared;  1: Reset or SOP* message transmission not sent due to incoming receive message. TX buffer registers are empty.
Note: when TX_SOP_MSG_SUCCESS and TX_SOP_MSG_FAILED interrupt are set to 1 both, it indicates the HARD_RST or 
CABLE_HARD_RST signal is sent done by PHY.
*/
#ifndef TX_SOP_MSG_FAILED
#define TX_SOP_MSG_FAILED
#endif
#define DPM_INT_STATUS_REG_TX_SOP_MSG_FAILED            (0x01)
#define DPM_INT_STATUS_REG_TX_SOP_MSG_FAILED_WTH        (0x01)
#define DPM_INT_STATUS_REG_TX_SOP_MSG_FAILED_FLDSET     (0x00000002)
#define DPM_INT_STATUS_REG_TX_SOP_MSG_FAILED_FLDMSK     (0xFFFFFFFD)

/**
TX_SOP_MSG_DISCARD, RC, reset value(0x0)
0: cleared;  1: SOP* message transmission not successful, no good CRC response received. TX SOP* message buffer registers are empty.
*/
#ifndef TX_SOP_MSG_DISCARD
#define TX_SOP_MSG_DISCARD
#endif
#define DPM_INT_STATUS_REG_TX_SOP_MSG_DISCARD           (0x00)
#define DPM_INT_STATUS_REG_TX_SOP_MSG_DISCARD_WTH       (0x01)
#define DPM_INT_STATUS_REG_TX_SOP_MSG_DISCARD_FLDSET    (0x00000001)
#define DPM_INT_STATUS_REG_TX_SOP_MSG_DISCARD_FLDMSK    (0xFFFFFFFE)


#define HW_TIMER_CTRL_REG                               (0x40000014)

/**
HW_TIMER3_BUSY, RW, reset value(0x0)
Hardware Timer 3 busy indication
*/
#ifndef HW_TIMER3_BUSY
#define HW_TIMER3_BUSY
#endif
#define HW_TIMER_CTRL_REG_HW_TIMER3_BUSY                (0x12)
#define HW_TIMER_CTRL_REG_HW_TIMER3_BUSY_WTH            (0x01)
#define HW_TIMER_CTRL_REG_HW_TIMER3_BUSY_FLDSET         (0x00040000)
#define HW_TIMER_CTRL_REG_HW_TIMER3_BUSY_FLDMSK         (0xFFFBFFFF)

/**
HW_TIMER2_BUSY, RW, reset value(0x0)
Hardware Timer 2 busy indication, SW could set this bit to 1 only when IN_CAPTURE1_EN is 0.
*/
#ifndef HW_TIMER2_BUSY
#define HW_TIMER2_BUSY
#endif
#define HW_TIMER_CTRL_REG_HW_TIMER2_BUSY                (0x11)
#define HW_TIMER_CTRL_REG_HW_TIMER2_BUSY_WTH            (0x01)
#define HW_TIMER_CTRL_REG_HW_TIMER2_BUSY_FLDSET         (0x00020000)
#define HW_TIMER_CTRL_REG_HW_TIMER2_BUSY_FLDMSK         (0xFFFDFFFF)

/**
HW_TIMER1_BUSY, RW, reset value(0x0)
Hardware Timer 1 busy indication, SW could set this bit to 1 only when IN_CAPTURE0_EN is 0.
*/
#ifndef HW_TIMER1_BUSY
#define HW_TIMER1_BUSY
#endif
#define HW_TIMER_CTRL_REG_HW_TIMER1_BUSY                (0x10)
#define HW_TIMER_CTRL_REG_HW_TIMER1_BUSY_WTH            (0x01)
#define HW_TIMER_CTRL_REG_HW_TIMER1_BUSY_FLDSET         (0x00010000)
#define HW_TIMER_CTRL_REG_HW_TIMER1_BUSY_FLDMSK         (0xFFFEFFFF)

/**
IN_CAPTURE1_CHN_SEL, RW, reset value(0x0)
Input capture GPIO channel selection
*/
#ifndef IN_CAPTURE1_CHN_SEL
#define IN_CAPTURE1_CHN_SEL
#endif
#define HW_TIMER_CTRL_REG_IN_CAPTURE1_CHN_SEL           (0x0B)
#define HW_TIMER_CTRL_REG_IN_CAPTURE1_CHN_SEL_WTH       (0x05)
#define HW_TIMER_CTRL_REG_IN_CAPTURE1_CHN_SEL_FLDSET    (0x0000F800)
#define HW_TIMER_CTRL_REG_IN_CAPTURE1_CHN_SEL_FLDMSK    (0xFFFF07FF)

/**
IN_CAPTURE1_EN, RW, reset value(0x0)
1: Input Capture enable 
*/
#ifndef IN_CAPTURE1_EN
#define IN_CAPTURE1_EN
#endif
#define HW_TIMER_CTRL_REG_IN_CAPTURE1_EN                (0x0A)
#define HW_TIMER_CTRL_REG_IN_CAPTURE1_EN_WTH            (0x01)
#define HW_TIMER_CTRL_REG_IN_CAPTURE1_EN_FLDSET         (0x00000400)
#define HW_TIMER_CTRL_REG_IN_CAPTURE1_EN_FLDMSK         (0xFFFFFBFF)

/**
IN_CAPTURE1_MODE, RW, reset value(0x0)
2'b00:  Capture the width between rising edges of input signal, the capture result will be latched into HW_TIMER2 registers
2'b01:  Capture the width between falling edges of input signal 
2'b10:  Capture the width from rising edge to falling edge of input signal 
2'b11:  Capture the width from falling edge to rising edge of input signal 
*/
#ifndef IN_CAPTURE1_MODE
#define IN_CAPTURE1_MODE
#endif
#define HW_TIMER_CTRL_REG_IN_CAPTURE1_MODE              (0x08)
#define HW_TIMER_CTRL_REG_IN_CAPTURE1_MODE_WTH          (0x02)
#define HW_TIMER_CTRL_REG_IN_CAPTURE1_MODE_FLDSET       (0x00000300)
#define HW_TIMER_CTRL_REG_IN_CAPTURE1_MODE_FLDMSK       (0xFFFFFCFF)

/**
IN_CAPTURE0_CHN_SEL, RW, reset value(0x0)
Input capture GPIO channel selection
*/
#ifndef IN_CAPTURE0_CHN_SEL
#define IN_CAPTURE0_CHN_SEL
#endif
#define HW_TIMER_CTRL_REG_IN_CAPTURE0_CHN_SEL           (0x03)
#define HW_TIMER_CTRL_REG_IN_CAPTURE0_CHN_SEL_WTH       (0x05)
#define HW_TIMER_CTRL_REG_IN_CAPTURE0_CHN_SEL_FLDSET    (0x000000F8)
#define HW_TIMER_CTRL_REG_IN_CAPTURE0_CHN_SEL_FLDMSK    (0xFFFFFF07)

/**
IN_CAPTURE0_EN, RW, reset value(0x0)
1: Input Capture enable 
*/
#ifndef IN_CAPTURE0_EN
#define IN_CAPTURE0_EN
#endif
#define HW_TIMER_CTRL_REG_IN_CAPTURE0_EN                (0x02)
#define HW_TIMER_CTRL_REG_IN_CAPTURE0_EN_WTH            (0x01)
#define HW_TIMER_CTRL_REG_IN_CAPTURE0_EN_FLDSET         (0x00000004)
#define HW_TIMER_CTRL_REG_IN_CAPTURE0_EN_FLDMSK         (0xFFFFFFFB)

/**
IN_CAPTURE0_MODE, RW, reset value(0x0)
2'b00:  Capture the width between rising edges of input signal, the capture result will be latched into HW_TIMER1 registers 
2'b01:  Capture the width between falling edges of input signal 
2'b10:  Capture the width from rising edge to falling edge of input signal 
2'b11:  Capture the width from falling edge to rising edge of input signal 
*/
#ifndef IN_CAPTURE0_MODE
#define IN_CAPTURE0_MODE
#endif
#define HW_TIMER_CTRL_REG_IN_CAPTURE0_MODE              (0x00)
#define HW_TIMER_CTRL_REG_IN_CAPTURE0_MODE_WTH          (0x02)
#define HW_TIMER_CTRL_REG_IN_CAPTURE0_MODE_FLDSET       (0x00000003)
#define HW_TIMER_CTRL_REG_IN_CAPTURE0_MODE_FLDMSK       (0xFFFFFFFC)


#define HW_TIMER1_REG                                   (0x40000018)

/**
HW_TIMER1, RW, reset value(0x0)
Hardware Timer 1 or Input capture0 result, when in capture mode, this register is read only      
*/
#ifndef HW_TIMER1
#define HW_TIMER1
#endif
#define HW_TIMER1_REG_HW_TIMER1                         (0x00)
#define HW_TIMER1_REG_HW_TIMER1_WTH                     (0x20)
#define HW_TIMER1_REG_HW_TIMER1_FLDSET                  (0xFFFFFFFF)
#define HW_TIMER1_REG_HW_TIMER1_FLDMSK                  (0x00000000)


#define HW_TIMER2_REG                                   (0x4000001C)

/**
HW_TIMER2, RW, reset value(0x0)
Hardware Timer 2 or input capture1 result, when in capture mode, this register is read only                
*/
#ifndef HW_TIMER2
#define HW_TIMER2
#endif
#define HW_TIMER2_REG_HW_TIMER2                         (0x00)
#define HW_TIMER2_REG_HW_TIMER2_WTH                     (0x20)
#define HW_TIMER2_REG_HW_TIMER2_FLDSET                  (0xFFFFFFFF)
#define HW_TIMER2_REG_HW_TIMER2_FLDMSK                  (0x00000000)


#define HW_TIMER3_REG                                   (0x40000020)

/**
HW_TIMER3, RW, reset value(0x0)
Hardware Timer 3, when chip work in capture mode, this register is read only and used to store hard reset signal time stamp.          
*/
#ifndef HW_TIMER3
#define HW_TIMER3
#endif
#define HW_TIMER3_REG_HW_TIMER3                         (0x00)
#define HW_TIMER3_REG_HW_TIMER3_WTH                     (0x20)
#define HW_TIMER3_REG_HW_TIMER3_FLDSET                  (0xFFFFFFFF)
#define HW_TIMER3_REG_HW_TIMER3_FLDMSK                  (0x00000000)


#define BIT_PERIOD_REG                                  (0x40000024)

/**
BIT_PERIOD, RW, reset value(0x6E)
BMC BIT PERIOD Setting:
Cycle number of sys_clk

*/
#ifndef BIT_PERIOD
#define BIT_PERIOD
#endif
#define BIT_PERIOD_REG_BIT_PERIOD                       (0x00)
#define BIT_PERIOD_REG_BIT_PERIOD_WTH                   (0x0A)
#define BIT_PERIOD_REG_BIT_PERIOD_FLDSET                (0x000003FF)
#define BIT_PERIOD_REG_BIT_PERIOD_FLDMSK                (0xFFFFFC00)


#define DMA_BUFF_REG0                                   (0x4000004C)

/**
TX_MSG_NUM, RW, reset value(0x0)
*/
#ifndef TX_MSG_NUM
#define TX_MSG_NUM
#endif
#define DMA_BUFF_REG0_TX_MSG_NUM                        (0x0C)
#define DMA_BUFF_REG0_TX_MSG_NUM_WTH                    (0x01)
#define DMA_BUFF_REG0_TX_MSG_NUM_FLDSET                 (0x00001000)
#define DMA_BUFF_REG0_TX_MSG_NUM_FLDMSK                 (0xFFFFEFFF)

/**
TX_MSG_SOP_TYPE, RW, reset value(0x0)
*/
#ifndef TX_MSG_SOP_TYPE
#define TX_MSG_SOP_TYPE
#endif
#define DMA_BUFF_REG0_TX_MSG_SOP_TYPE                   (0x09)
#define DMA_BUFF_REG0_TX_MSG_SOP_TYPE_WTH               (0x03)
#define DMA_BUFF_REG0_TX_MSG_SOP_TYPE_FLDSET            (0x00000E00)
#define DMA_BUFF_REG0_TX_MSG_SOP_TYPE_FLDMSK            (0xFFFFF1FF)

/**
TX_MSG_LEN, RW, reset value(0x0)
*/
#ifndef TX_MSG_LEN
#define TX_MSG_LEN
#endif
#define DMA_BUFF_REG0_TX_MSG_LEN                        (0x00)
#define DMA_BUFF_REG0_TX_MSG_LEN_WTH                    (0x09)
#define DMA_BUFF_REG0_TX_MSG_LEN_FLDSET                 (0x000001FF)
#define DMA_BUFF_REG0_TX_MSG_LEN_FLDMSK                 (0xFFFFFE00)


#define DMA_BUFF_REG1                                   (0x40000050)

/**
DMA_TX_DATA_START_ADDR, RW, reset value(0x0)
*/
#ifndef DMA_TX_DATA_START_ADDR
#define DMA_TX_DATA_START_ADDR
#endif
#define DMA_BUFF_REG1_DMA_TX_DATA_START_ADDR            (0x00)
#define DMA_BUFF_REG1_DMA_TX_DATA_START_ADDR_WTH        (0x20)
#define DMA_BUFF_REG1_DMA_TX_DATA_START_ADDR_FLDSET     (0xFFFFFFFF)
#define DMA_BUFF_REG1_DMA_TX_DATA_START_ADDR_FLDMSK     (0x00000000)


#define DMA_BUFF_REG2                                   (0x40000054)

/**
DMA_TX_DATA_END_ADDR, RW, reset value(0x0)
*/
#ifndef DMA_TX_DATA_END_ADDR
#define DMA_TX_DATA_END_ADDR
#endif
#define DMA_BUFF_REG2_DMA_TX_DATA_END_ADDR              (0x00)
#define DMA_BUFF_REG2_DMA_TX_DATA_END_ADDR_WTH          (0x20)
#define DMA_BUFF_REG2_DMA_TX_DATA_END_ADDR_FLDSET       (0xFFFFFFFF)
#define DMA_BUFF_REG2_DMA_TX_DATA_END_ADDR_FLDMSK       (0x00000000)


#define DMA_BUFF_REG3                                   (0x40000058)

/**
DMA_TX_DATA_RPTR, RO, reset value(0x0)
*/
#ifndef DMA_TX_DATA_RPTR
#define DMA_TX_DATA_RPTR
#endif
#define DMA_BUFF_REG3_DMA_TX_DATA_RPTR                  (0x00)
#define DMA_BUFF_REG3_DMA_TX_DATA_RPTR_WTH              (0x20)
#define DMA_BUFF_REG3_DMA_TX_DATA_RPTR_FLDSET           (0xFFFFFFFF)
#define DMA_BUFF_REG3_DMA_TX_DATA_RPTR_FLDMSK           (0x00000000)


#define DMA_BUFF_REG4                                   (0x4000005C)

/**
RX_BUFF_FULL_THRES, RW, reset value(0x10)
RX_BUFF_FULL threshold, SW could configure how many rx message number could trigger the RX_BUFF_FULL event 
*/
#ifndef RX_BUFF_FULL_THRES
#define RX_BUFF_FULL_THRES
#endif
#define DMA_BUFF_REG4_RX_BUFF_FULL_THRES                (0x14)
#define DMA_BUFF_REG4_RX_BUFF_FULL_THRES_WTH            (0x05)
#define DMA_BUFF_REG4_RX_BUFF_FULL_THRES_FLDSET         (0x01F00000)
#define DMA_BUFF_REG4_RX_BUFF_FULL_THRES_FLDMSK         (0xFE0FFFFF)

/**
RX_MSG_NUM, RO, reset value(0x0)
*/
#ifndef RX_MSG_NUM
#define RX_MSG_NUM
#endif
#define DMA_BUFF_REG4_RX_MSG_NUM                        (0x0C)
#define DMA_BUFF_REG4_RX_MSG_NUM_WTH                    (0x05)
#define DMA_BUFF_REG4_RX_MSG_NUM_FLDSET                 (0x0001F000)
#define DMA_BUFF_REG4_RX_MSG_NUM_FLDMSK                 (0xFFFE0FFF)

/**
RX_MSG_SOP_TYPE, RO, reset value(0x0)
*/
#ifndef RX_MSG_SOP_TYPE
#define RX_MSG_SOP_TYPE
#endif
#define DMA_BUFF_REG4_RX_MSG_SOP_TYPE                   (0x09)
#define DMA_BUFF_REG4_RX_MSG_SOP_TYPE_WTH               (0x03)
#define DMA_BUFF_REG4_RX_MSG_SOP_TYPE_FLDSET            (0x00000E00)
#define DMA_BUFF_REG4_RX_MSG_SOP_TYPE_FLDMSK            (0xFFFFF1FF)

/**
RX_MSG_LEN, RO, reset value(0x0)
*/
#ifndef RX_MSG_LEN
#define RX_MSG_LEN
#endif
#define DMA_BUFF_REG4_RX_MSG_LEN                        (0x00)
#define DMA_BUFF_REG4_RX_MSG_LEN_WTH                    (0x09)
#define DMA_BUFF_REG4_RX_MSG_LEN_FLDSET                 (0x000001FF)
#define DMA_BUFF_REG4_RX_MSG_LEN_FLDMSK                 (0xFFFFFE00)


#define DMA_BUFF_REG5                                   (0x40000060)

/**
DMA_RX_DATA_START_ADDR, RW, reset value(0x0)
*/
#ifndef DMA_RX_DATA_START_ADDR
#define DMA_RX_DATA_START_ADDR
#endif
#define DMA_BUFF_REG5_DMA_RX_DATA_START_ADDR            (0x00)
#define DMA_BUFF_REG5_DMA_RX_DATA_START_ADDR_WTH        (0x20)
#define DMA_BUFF_REG5_DMA_RX_DATA_START_ADDR_FLDSET     (0xFFFFFFFF)
#define DMA_BUFF_REG5_DMA_RX_DATA_START_ADDR_FLDMSK     (0x00000000)


#define DMA_BUFF_REG6                                   (0x40000064)

/**
DMA_RX_DATA_END_ADDR, RW, reset value(0x0)
*/
#ifndef DMA_RX_DATA_END_ADDR
#define DMA_RX_DATA_END_ADDR
#endif
#define DMA_BUFF_REG6_DMA_RX_DATA_END_ADDR              (0x00)
#define DMA_BUFF_REG6_DMA_RX_DATA_END_ADDR_WTH          (0x20)
#define DMA_BUFF_REG6_DMA_RX_DATA_END_ADDR_FLDSET       (0xFFFFFFFF)
#define DMA_BUFF_REG6_DMA_RX_DATA_END_ADDR_FLDMSK       (0x00000000)


#define DMA_BUFF_REG7                                   (0x40000068)

/**
DMA_RX_DATA_WPTR, RO, reset value(0x0)
*/
#ifndef DMA_RX_DATA_WPTR
#define DMA_RX_DATA_WPTR
#endif
#define DMA_BUFF_REG7_DMA_RX_DATA_WPTR                  (0x00)
#define DMA_BUFF_REG7_DMA_RX_DATA_WPTR_WTH              (0x20)
#define DMA_BUFF_REG7_DMA_RX_DATA_WPTR_FLDSET           (0xFFFFFFFF)
#define DMA_BUFF_REG7_DMA_RX_DATA_WPTR_FLDMSK           (0x00000000)


#define TEST_BUS_REG                                    (0x400000B0)

/**
HW_DEBUG_SIGNALS, RO, reset value(0x0)
test_bus
*/
#ifndef HW_DEBUG_SIGNALS
#define HW_DEBUG_SIGNALS
#endif
#define TEST_BUS_REG_HW_DEBUG_SIGNALS                   (0x10)
#define TEST_BUS_REG_HW_DEBUG_SIGNALS_WTH               (0x08)
#define TEST_BUS_REG_HW_DEBUG_SIGNALS_FLDSET            (0x00FF0000)
#define TEST_BUS_REG_HW_DEBUG_SIGNALS_FLDMSK            (0xFF00FFFF)

/**
PRL_HR_STATE, RO, reset value(0X0)
*/
#ifndef PRL_HR_STATE
#define PRL_HR_STATE
#endif
#define TEST_BUS_REG_PRL_HR_STATE                       (0x08)
#define TEST_BUS_REG_PRL_HR_STATE_WTH                   (0x03)
#define TEST_BUS_REG_PRL_HR_STATE_FLDSET                (0x00000700)
#define TEST_BUS_REG_PRL_HR_STATE_FLDMSK                (0xFFFFF8FF)

/**
PRL_RX_STATE, RO, reset value(0x0)
*/
#ifndef PRL_RX_STATE
#define PRL_RX_STATE
#endif
#define TEST_BUS_REG_PRL_RX_STATE                       (0x04)
#define TEST_BUS_REG_PRL_RX_STATE_WTH                   (0x02)
#define TEST_BUS_REG_PRL_RX_STATE_FLDSET                (0x00000030)
#define TEST_BUS_REG_PRL_RX_STATE_FLDMSK                (0xFFFFFFCF)

/**
PRL_TX_STATE, RO, reset value(0x0)
*/
#ifndef PRL_TX_STATE
#define PRL_TX_STATE
#endif
#define TEST_BUS_REG_PRL_TX_STATE                       (0x00)
#define TEST_BUS_REG_PRL_TX_STATE_WTH                   (0x04)
#define TEST_BUS_REG_PRL_TX_STATE_FLDSET                (0x0000000F)
#define TEST_BUS_REG_PRL_TX_STATE_FLDMSK                (0xFFFFFFF0)


#define TIMER_CFG_REG                                   (0x400000B4)

/**
T_TRANSMIT, RW, reset value(0x1923)
good CRC message should be sent in tTransmit, maximum value is 195 us.
*/
#ifndef T_TRANSMIT
#define T_TRANSMIT
#endif
#define TIMER_CFG_REG_T_TRANSMIT                        (0x10)
#define TIMER_CFG_REG_T_TRANSMIT_WTH                    (0x10)
#define TIMER_CFG_REG_T_TRANSMIT_FLDSET                 (0xFFFF0000)
#define TIMER_CFG_REG_T_TRANSMIT_FLDMSK                 (0x0000FFFF)

/**
T_RECEIVE, RW, reset value(0x8DCC)
good CRC message receive time out value is 1.1 ms.
*/
#ifndef T_RECEIVE
#define T_RECEIVE
#endif
#define TIMER_CFG_REG_T_RECEIVE                         (0x00)
#define TIMER_CFG_REG_T_RECEIVE_WTH                     (0x10)
#define TIMER_CFG_REG_T_RECEIVE_FLDSET                  (0x0000FFFF)
#define TIMER_CFG_REG_T_RECEIVE_FLDMSK                  (0xFFFF0000)


#define HR_TIMER_CFG_REG                                (0x400000B8)

/**
T_FRS_DETECT, RW, reset value(0x3DD)
FRS rx detected timer, 30 us
*/
#ifndef T_FRS_DETECT
#define T_FRS_DETECT
#endif
#define HR_TIMER_CFG_REG_T_FRS_DETECT                   (0x14)
#define HR_TIMER_CFG_REG_T_FRS_DETECT_WTH               (0x0B)
#define HR_TIMER_CFG_REG_T_FRS_DETECT_FLDSET            (0x7FF00000)
#define HR_TIMER_CFG_REG_T_FRS_DETECT_FLDMSK            (0x800FFFFF)

/**
T_HR_COMPLT, RW, reset value(0x28488)
Hard Reset complete Timer, maximum 5 ms
*/
#ifndef T_HR_COMPLT
#define T_HR_COMPLT
#endif
#define HR_TIMER_CFG_REG_T_HR_COMPLT                    (0x00)
#define HR_TIMER_CFG_REG_T_HR_COMPLT_WTH                (0x12)
#define HR_TIMER_CFG_REG_T_HR_COMPLT_FLDSET             (0x0003FFFF)
#define HR_TIMER_CFG_REG_T_HR_COMPLT_FLDMSK             (0xFFFC0000)


#define CC_IO_CFG_REG                                   (0x400000BC)

/**
CC_IO_TEST_MODE, RW, reset value(0x0)
1: CC IO test mode
*/
#ifndef CC_IO_TEST_MODE
#define CC_IO_TEST_MODE
#endif
#define CC_IO_CFG_REG_CC_IO_TEST_MODE                   (0x1F)
#define CC_IO_CFG_REG_CC_IO_TEST_MODE_WTH               (0x01)
#define CC_IO_CFG_REG_CC_IO_TEST_MODE_FLDSET            (0x80000000)
#define CC_IO_CFG_REG_CC_IO_TEST_MODE_FLDMSK            (0x7FFFFFFF)

/**
CC_IO_TEST_OE, RW, reset value(0x0)
CC IO test mode output enable, 1: output 0: input
*/
#ifndef CC_IO_TEST_OE
#define CC_IO_TEST_OE
#endif
#define CC_IO_CFG_REG_CC_IO_TEST_OE                     (0x1E)
#define CC_IO_CFG_REG_CC_IO_TEST_OE_WTH                 (0x01)
#define CC_IO_CFG_REG_CC_IO_TEST_OE_FLDSET              (0x40000000)
#define CC_IO_CFG_REG_CC_IO_TEST_OE_FLDMSK              (0xBFFFFFFF)

/**
CC2_CEN, RW, reset value(0x1)
Comparator input enable, 1'b1 : Comparator Mode, 1'b0 : Common mode.
*/
#ifndef CC2_CEN
#define CC2_CEN
#endif
#define CC_IO_CFG_REG_CC2_CEN                           (0x11)
#define CC_IO_CFG_REG_CC2_CEN_WTH                       (0x01)
#define CC_IO_CFG_REG_CC2_CEN_FLDSET                    (0x00020000)
#define CC_IO_CFG_REG_CC2_CEN_FLDMSK                    (0xFFFDFFFF)

/**
CC1_CEN, RW, reset value(0x1)
Comparator input enable, 1'b1 : Comparator Mode, 1'b0 : Common mode.
*/
#ifndef CC1_CEN
#define CC1_CEN
#endif
#define CC_IO_CFG_REG_CC1_CEN                           (0x10)
#define CC_IO_CFG_REG_CC1_CEN_WTH                       (0x01)
#define CC_IO_CFG_REG_CC1_CEN_FLDSET                    (0x00010000)
#define CC_IO_CFG_REG_CC1_CEN_FLDMSK                    (0xFFFEFFFF)

/**
CC2_REFSEL, RW, reset value(0x1)
cc2 VREF select 
2'b00 : 0.4375 V
2'b01 : 0.5625 V
2'b10 : 0.6875 V
2'b11 : Not used.
*/
#ifndef CC2_REFSEL
#define CC2_REFSEL
#endif
#define CC_IO_CFG_REG_CC2_REFSEL                        (0x0E)
#define CC_IO_CFG_REG_CC2_REFSEL_WTH                    (0x02)
#define CC_IO_CFG_REG_CC2_REFSEL_FLDSET                 (0x0000C000)
#define CC_IO_CFG_REG_CC2_REFSEL_FLDMSK                 (0xFFFF3FFF)

/**
CC1_REFSEL, RW, reset value(0x1)
cc1 VREF select 
2'b00 : 0.4375 V
2'b01 : 0.5625 V
2'b10 : 0.6875 V
2'b11 : Not used.
*/
#ifndef CC1_REFSEL
#define CC1_REFSEL
#endif
#define CC_IO_CFG_REG_CC1_REFSEL                        (0x0C)
#define CC_IO_CFG_REG_CC1_REFSEL_WTH                    (0x02)
#define CC_IO_CFG_REG_CC1_REFSEL_FLDSET                 (0x00003000)
#define CC_IO_CFG_REG_CC1_REFSEL_FLDMSK                 (0xFFFFCFFF)

/**
CC2_EGCTRL, RW, reset value(0x2)
cc2 output signal edge control
2'b00 : 100 ns
2'b01 : 200 ns
2'b10 : 300 ns
2'b11 : 400 ns
*/
#ifndef CC2_EGCTRL
#define CC2_EGCTRL
#endif
#define CC_IO_CFG_REG_CC2_EGCTRL                        (0x0A)
#define CC_IO_CFG_REG_CC2_EGCTRL_WTH                    (0x02)
#define CC_IO_CFG_REG_CC2_EGCTRL_FLDSET                 (0x00000C00)
#define CC_IO_CFG_REG_CC2_EGCTRL_FLDMSK                 (0xFFFFF3FF)

/**
CC1_EGCTRL, RW, reset value(0x2)
cc1 output signal edge control
2'b00 : 100 ns
2'b01 : 200 ns
2'b10 : 300 ns
2'b11 : 400 ns
*/
#ifndef CC1_EGCTRL
#define CC1_EGCTRL
#endif
#define CC_IO_CFG_REG_CC1_EGCTRL                        (0x08)
#define CC_IO_CFG_REG_CC1_EGCTRL_WTH                    (0x02)
#define CC_IO_CFG_REG_CC1_EGCTRL_FLDSET                 (0x00000300)
#define CC_IO_CFG_REG_CC1_EGCTRL_FLDMSK                 (0xFFFFFCFF)

/**
CC2_ES, RW, reset value(0x4)
cc IO output driver resistance, 
3'b100 : 50 ohm, 
3'b011 : 62.5 ohm,
3'b101 : 41.6 ohm,
3'b110 : 35.6 ohm,
3'b111 : 31.2 ohm
*/
#ifndef CC2_ES
#define CC2_ES
#endif
#define CC_IO_CFG_REG_CC2_ES                            (0x04)
#define CC_IO_CFG_REG_CC2_ES_WTH                        (0x03)
#define CC_IO_CFG_REG_CC2_ES_FLDSET                     (0x00000070)
#define CC_IO_CFG_REG_CC2_ES_FLDMSK                     (0xFFFFFF8F)

/**
CC1_ES, RW, reset value(0x4)
cc IO output driver resistance, 
3'b100 : 50 ohm, 
3'b011 : 62.5 ohm,
3'b101 : 41.6 ohm,
3'b110 : 35.6 ohm,
3'b111 : 31.2 ohm
*/
#ifndef CC1_ES
#define CC1_ES
#endif
#define CC_IO_CFG_REG_CC1_ES                            (0x00)
#define CC_IO_CFG_REG_CC1_ES_WTH                        (0x03)
#define CC_IO_CFG_REG_CC1_ES_FLDSET                     (0x00000007)
#define CC_IO_CFG_REG_CC1_ES_FLDMSK                     (0xFFFFFFF8)



#endif /* #ifndef __REG_DEF_PD_H_ */

