/**
 * \file    sc8812_reg_defs.h
 * \brief   register definitions for SC8812A
 * 
 * \par     Copyright (c) 2018 UWE Technologies Corp., Ltd. All Rights Reserved.
 * \author  James
 * \date    2018-01-05
 * \version 
 * 
 * \history 
 *  Date        Note
 *  2018-01-05  Original Creation
 * 
 */

#ifndef __SC8812_REG_DEFS_H_
#define __SC8812_REG_DEFS_H_


/** \name  Register access type definition
 * \{ 
 */
#define RO      (0) ///< Read only
#define RC      (1) ///< Read and clear
#define RW      (2) ///< Read and write
#define WC      (3) ///< Write and clear
/** \} */


#define SYS_BAT_BASE_ADDR                                (0xE8)



#define VBAT_SET_REG                                    (0x00)

/**
IRCOMP, RW, reset value(0x0)
Battery IR compensation setting:
00: 0 mΩ (default)
01: 20 mΩ
10: 40 mΩ
11: 80 mΩ
*/
#ifndef IRCOMP
#define IRCOMP
#endif
#define VBAT_SET_REG_IRCOMP                             (0x06)
#define VBAT_SET_REG_IRCOMP_WTH                         (0x02)
#define VBAT_SET_REG_IRCOMP_FLDSET                      (0xC0)
#define VBAT_SET_REG_IRCOMP_FLDMSK                      (0x3F)
#define VBAT_SET_REG_IRCOMP_ACCESS                      RW

/**
VBAT_SEL, RW, reset value(0x0)
VBAT voltage setting selection:
0: internal setting (default)
1: external setting
*/
#ifndef VBAT_SEL
#define VBAT_SEL
#endif
#define VBAT_SET_REG_VBAT_SEL                           (0x05)
#define VBAT_SET_REG_VBAT_SEL_WTH                       (0x01)
#define VBAT_SET_REG_VBAT_SEL_FLDSET                    (0x20)
#define VBAT_SET_REG_VBAT_SEL_FLDMSK                    (0xDF)
#define VBAT_SET_REG_VBAT_SEL_ACCESS                    RW

/**
CSEL, RW, reset value(0x0)
Battery cell selection, only valid for internal VBAT voltage setting
00: 1S battery (default)
01: 2S battery
10: 3S battery
11: 4S battery
*/
#ifndef CSEL
#define CSEL
#endif
#define VBAT_SET_REG_CSEL                               (0x03)
#define VBAT_SET_REG_CSEL_WTH                           (0x02)
#define VBAT_SET_REG_CSEL_FLDSET                        (0x18)
#define VBAT_SET_REG_CSEL_FLDMSK                        (0xE7)
#define VBAT_SET_REG_CSEL_ACCESS                        RW

/**
VCELL_SET, RW, reset value(0x1)
Battery voltage setting per cell, only valid for internal VBAT voltage setting
000: 4.1V
001: 4.2V (default)
010: 4.25V
011: 4.3V
100: 4.35V
101: 4.4V
110: 4.45V
111: 4.5V
*/
#ifndef VCELL_SET
#define VCELL_SET
#endif
#define VBAT_SET_REG_VCELL_SET                          (0x00)
#define VBAT_SET_REG_VCELL_SET_WTH                      (0x03)
#define VBAT_SET_REG_VCELL_SET_FLDSET                   (0x07)
#define VBAT_SET_REG_VCELL_SET_FLDMSK                   (0xF8)
#define VBAT_SET_REG_VCELL_SET_ACCESS                   RW

#define VBAT_SET_REG_ACCESS                             RW
#define VBAT_SET_REG_FIELD_COUNT                        (4)


#define VBUSREF_I_SET_REG                               (0x01)

/**
VBUSREF_I_SET, RW, reset value(0x31)
Reference voltage programming for internal VBUS voltage setting.
When FB_SEL = 0 (internal VBUS setting), set the highest 8-bit of the reference voltage for VBUS (total 10-bit programming).
The internal reference voltage is calculated as VBUSREF_I = (4 x VBUSREF_I_SET + VBUSREF_I_SET2 + 1) x 2 mV
The VBUS output voltage is calculated as VBUS = VBUSREF_I x VBUS_RATIO
VBUSREF_I_SET range: 0 ~ 255
0000 0000: 0
0000 0001: 1
0000 0010: 2
….
0011 0001: 49 (default)
….
1111 1111: 255
The default reference voltage is (4 x 49 +3+1) x 2 mV = 400 mV; the default VBUS output voltage with FB_SEL = 0 is 400mV x 12.5 = 5V
*/
#ifndef VBUSREF_I_SET
#define VBUSREF_I_SET
#endif
#define VBUSREF_I_SET_REG_VBUSREF_I_SET                 (0x00)
#define VBUSREF_I_SET_REG_VBUSREF_I_SET_WTH             (0x08)
#define VBUSREF_I_SET_REG_VBUSREF_I_SET_FLDSET          (0xFF)
#define VBUSREF_I_SET_REG_VBUSREF_I_SET_FLDMSK          (0x00)
#define VBUSREF_I_SET_REG_VBUSREF_I_SET_ACCESS          RW

#define VBUSREF_I_SET_REG_ACCESS                        RW
#define VBUSREF_I_SET_REG_FIELD_COUNT                   (1)


#define VBUSREF_I_SET2_REG                              (0x02)

/**
VBUSREF_I_SET2, RW, reset value(0x3)
Reference voltage programming for internal VBUS voltage setting.
When FB_SEL = 0 (internal VBUS setting), set the lowest 2-bit of the reference voltage for VBUS (total 10-bit programming).
The internal reference voltage is calculated as VBUSREF_I = (4 x VBUSREF_I_SET + VBUSREF_I_SET2 + 1) x 2 mV
The VBUS output voltage is calculated as VBUS = VBUSREF_I x VBUS_RATIO
VBUSREF_I_SET2 range: 0 ~ 3
00: 0
01: 1
10: 2
11: 3 (default)
*/
#ifndef VBUSREF_I_SET2
#define VBUSREF_I_SET2
#endif
#define VBUSREF_I_SET2_REG_VBUSREF_I_SET2               (0x06)
#define VBUSREF_I_SET2_REG_VBUSREF_I_SET2_WTH           (0x02)
#define VBUSREF_I_SET2_REG_VBUSREF_I_SET2_FLDSET        (0xC0)
#define VBUSREF_I_SET2_REG_VBUSREF_I_SET2_FLDMSK        (0x3F)
#define VBUSREF_I_SET2_REG_VBUSREF_I_SET2_ACCESS        RW

#define VBUSREF_I_SET2_REG_ACCESS                       RW
#define VBUSREF_I_SET2_REG_FIELD_COUNT                  (2)


#define VBUSREF_E_SET_REG                               (0x03)

/**
VBUSREF_E_SET, RW, reset value(0x7C)
Reference voltage programming for external VBUS voltage setting.
When FB_SEL = 1 (external VBUS setting), set the highest 8-bit of the reference voltage for VBUS (total 10-bit programming).
The external reference voltage is calculated as VBUSREF_E = (4 x VBUSREF_E_SET+VBUSREF_E_SET2+1) x 2mV
The VBUS output voltage is calculated as VBUS = VBUSREF_E x (1+RUP/RDOWM)
VBUSREF_E_SET range: 0 ~ 255
0000 0000: 0
0000 0001: 1
0000 0010: 2
….
0111 1100: 124 (default)
….
1111 1111: 255
The default reference voltage is (4 x 124 +3 +1) x 2 mV = 1 V
*/
#ifndef VBUSREF_E_SET
#define VBUSREF_E_SET
#endif
#define VBUSREF_E_SET_REG_VBUSREF_E_SET                 (0x00)
#define VBUSREF_E_SET_REG_VBUSREF_E_SET_WTH             (0x08)
#define VBUSREF_E_SET_REG_VBUSREF_E_SET_FLDSET          (0xFF)
#define VBUSREF_E_SET_REG_VBUSREF_E_SET_FLDMSK          (0x00)
#define VBUSREF_E_SET_REG_VBUSREF_E_SET_ACCESS          RW

#define VBUSREF_E_SET_REG_ACCESS                        RW
#define VBUSREF_E_SET_REG_FIELD_COUNT                   (1)


#define VBUSREF_E_SET2_REG                              (0x04)

/**
VBUSREF_E_SET2, RW, reset value(0x3)
Reference voltage programming for external VBUS voltage setting.
When FB_SEL = 1 (external VBUS setting), set the lowest 2-bit of the reference voltage for VBUS (total 10-bit programming).
The external reference voltage is calculated as VBUSREF_E = (4 x VBUSREF_E_SET+VBUSREF_E_SET2+1) x 2mV
The VBUS output voltage is calculated as VBUS = VBUSREF_E x (1+RUP/RDOWM)
VBUSREF_E_SET2 range: 0 ~ 3
00: 0
01: 1
10: 2
11: 3 (default)
*/
#ifndef VBUSREF_E_SET2
#define VBUSREF_E_SET2
#endif
#define VBUSREF_E_SET2_REG_VBUSREF_E_SET2               (0x06)
#define VBUSREF_E_SET2_REG_VBUSREF_E_SET2_WTH           (0x02)
#define VBUSREF_E_SET2_REG_VBUSREF_E_SET2_FLDSET        (0xC0)
#define VBUSREF_E_SET2_REG_VBUSREF_E_SET2_FLDMSK        (0x3F)
#define VBUSREF_E_SET2_REG_VBUSREF_E_SET2_ACCESS        RW

#define VBUSREF_E_SET2_REG_ACCESS                       RW
#define VBUSREF_E_SET2_REG_FIELD_COUNT                  (2)


#define IBUS_LIM_SET_REG                                (0x05)

/**
IBUS_LIM_SET, RW, reset value(0xFF)
Set IBUS current limit, which is valid for both charging and discharging modes. IBUS_LIM (A) = (IBUS_LIM_SET +1)/256 × IBUS_RATIO ×10 mΩ/RS1
RS1 is the current sense resistor at VBUS side.
IBUS_LIM_SET range: 0 ~ 255
0000 0000: 0
0000 0001: 1
0000 0010: 2
…
1111 1111: 255 (default)
E.g., if RS1 = 10 mΩ, the default IBUS current limit is
(255+1)/256 x 3 x 10 mΩ / 10 mΩ = 3 A
*/
#ifndef IBUS_LIM_SET
#define IBUS_LIM_SET
#endif
#define IBUS_LIM_SET_REG_IBUS_LIM_SET                   (0x00)
#define IBUS_LIM_SET_REG_IBUS_LIM_SET_WTH               (0x08)
#define IBUS_LIM_SET_REG_IBUS_LIM_SET_FLDSET            (0xFF)
#define IBUS_LIM_SET_REG_IBUS_LIM_SET_FLDMSK            (0x00)
#define IBUS_LIM_SET_REG_IBUS_LIM_SET_ACCESS            RW

#define IBUS_LIM_SET_REG_ACCESS                         RW
#define IBUS_LIM_SET_REG_FIELD_COUNT                    (1)


#define IBAT_LIM_SET_REG                                (0x06)

/**
IBAT_LIM_SET, RW, reset value(0xFF)
Set IBAT current limit, which is valid for both charging and discharging modes. IBAT_LIM (A) = (IBAT_LIM_SET+1)/256 × IBAT_RATIO ×10 mΩ/RS2
RS2 is the current sense resistor at VBAT side.
IBAT_LIM_SET range: 0 ~ 255
0000 0000: 0
0000 0001: 1
0000 0010: 2
…
1111 1111: 255 (default)
E.g., if RS2 = 10 mΩ, the default IBAT current limit is
(255+1)/256 x 12 x 10 mΩ / 10 mΩ = 12 A
*/
#ifndef IBAT_LIM_SET
#define IBAT_LIM_SET
#endif
#define IBAT_LIM_SET_REG_IBAT_LIM_SET                   (0x00)
#define IBAT_LIM_SET_REG_IBAT_LIM_SET_WTH               (0x08)
#define IBAT_LIM_SET_REG_IBAT_LIM_SET_FLDSET            (0xFF)
#define IBAT_LIM_SET_REG_IBAT_LIM_SET_FLDMSK            (0x00)
#define IBAT_LIM_SET_REG_IBAT_LIM_SET_ACCESS            RW

#define IBAT_LIM_SET_REG_ACCESS                         RW
#define IBAT_LIM_SET_REG_FIELD_COUNT                    (1)


#define VINREG_SET                                      (0x07)

/**
VINREG_SET, RW, reset value(0x2C)
Set VINREG reference voltage for charging mode. VINREG = （VINREG_SET+1) × VINREG_RATIO (mV)
VINREG_SET range: 0 ~ 255
0000 0000: 0
0000 0001: 1
…
0010 1100: 44 (default)
…
1111 1111: 255
If VINREG_RATIO = 1 (40x), the default VINREG voltage is 1.8V, and the maximum VINREG voltage which can be set is 10.24V;
If VINREG_RATIO = 0 (100x), the default VINREG voltage is 4.5V, and the maximum VINREG voltage which can be set is 25.6V.
*/
#ifndef VINREG_SET
#define VINREG_SET
#endif
#define VINREG_SET_VINREG_SET                           (0x00)
#define VINREG_SET_VINREG_SET_WTH                       (0x08)
#define VINREG_SET_VINREG_SET_FLDSET                    (0xFF)
#define VINREG_SET_VINREG_SET_FLDMSK                    (0x00)
#define VINREG_SET_VINREG_SET_ACCESS                    RW

#define VINREG_SET_ACCESS                               RW
#define VINREG_SET_FIELD_COUNT                          (1)


#define RATIO_REG                                       (0x08)

/**
RSEN_SET, RW, reset value(0x0)
Current sense resistor value bit. Set this bit according to external current sense resistor value.
00: 10 mΩ (default)
01: 5 mΩ
10: 2 mΩ
11: <2 mΩ
If the two external current sense resistors have different values, choose the value between the two or choose the lower value. For example, if RS1 = 10 mΩ, RS2 = 5 mΩ, choose 5 mΩ bit.
*/
#ifndef RSEN_SET
#define RSEN_SET
#endif
#define RATIO_REG_RSEN_SET                              (0x06)
#define RATIO_REG_RSEN_SET_WTH                          (0x02)
#define RATIO_REG_RSEN_SET_FLDSET                       (0xC0)
#define RATIO_REG_RSEN_SET_FLDMSK                       (0x3F)
#define RATIO_REG_RSEN_SET_ACCESS                       RW

/**
IBAT_RATIO, RW, reset value(0x0)
IBAT_LIM setting ratio
0: 6x
1: 12x (default)
*/
#ifndef IBAT_RATIO
#define IBAT_RATIO
#endif
#define RATIO_REG_IBAT_RATIO                            (0x04)
#define RATIO_REG_IBAT_RATIO_WTH                        (0x01)
#define RATIO_REG_IBAT_RATIO_FLDSET                     (0x10)
#define RATIO_REG_IBAT_RATIO_FLDMSK                     (0xEF)
#define RATIO_REG_IBAT_RATIO_ACCESS                     RW

/**
IBUS_RATIO, RW, reset value(0x2)
IBUS_LIM setting ratio
00: not allowed
01: 6x
10: 3x (default)
11: not allowed
*/
#ifndef IBUS_RATIO
#define IBUS_RATIO
#endif
#define RATIO_REG_IBUS_RATIO                            (0x02)
#define RATIO_REG_IBUS_RATIO_WTH                        (0x02)
#define RATIO_REG_IBUS_RATIO_FLDSET                     (0x0C)
#define RATIO_REG_IBUS_RATIO_FLDMSK                     (0xF3)
#define RATIO_REG_IBUS_RATIO_ACCESS                     RW

/**
VBAT_MON_RATIO, RW, reset value(0x0)
Ratio setting for VBAT voltage monitor
0: 12.5x (default)
1: 5x
The battery voltage is monitored through ADC and can be calculated as below:
VBAT = (4 x VBAT_FB_VALUE + VBAT_FB_VALUE2 + 1) x VBAT_MON_RATIO x 2 mV
VBAT_FB_VALUE and VBAT_FB_VALUE2 are ADC register values.
For 1S and 2S battery applications (VBAT < 9V), set this bit to 1.
*/
#ifndef VBAT_MON_RATIO
#define VBAT_MON_RATIO
#endif
#define RATIO_REG_VBAT_MON_RATIO                        (0x01)
#define RATIO_REG_VBAT_MON_RATIO_WTH                    (0x01)
#define RATIO_REG_VBAT_MON_RATIO_FLDSET                 (0x02)
#define RATIO_REG_VBAT_MON_RATIO_FLDMSK                 (0xFD)
#define RATIO_REG_VBAT_MON_RATIO_ACCESS                 RW

/**
VBUS_RATIO, RW, reset value(0x0)
Set the ratio for VBUS voltage setting and VBUS voltage monitor.
0: 12.5x (default)
1: 5x
*/
#ifndef VBUS_RATIO
#define VBUS_RATIO
#endif
#define RATIO_REG_VBUS_RATIO                            (0x00)
#define RATIO_REG_VBUS_RATIO_WTH                        (0x01)
#define RATIO_REG_VBUS_RATIO_FLDSET                     (0x01)
#define RATIO_REG_VBUS_RATIO_FLDMSK                     (0xFE)
#define RATIO_REG_VBUS_RATIO_ACCESS                     RW

#define RATIO_REG_ACCESS                                RW
#define RATIO_REG_FIELD_COUNT                           (6)


#define CTRL0_SET_REG                                   (0x09)

/**
EN_OTG, RW, reset value(0x0)
Enable OTG operation
0: set the charger to work in charging mode (default)
1: set the charger to work in discharging mode
*/
#ifndef EN_OTG
#define EN_OTG
#endif
#define CTRL0_SET_REG_EN_OTG                            (0x07)
#define CTRL0_SET_REG_EN_OTG_WTH                        (0x01)
#define CTRL0_SET_REG_EN_OTG_FLDSET                     (0x80)
#define CTRL0_SET_REG_EN_OTG_FLDMSK                     (0x7F)
#define CTRL0_SET_REG_EN_OTG_ACCESS                     RW

/**
DIS_INDET, RW, reset value(0x0)
Disable load insertion detection
0: enable USB-A load insertion detection at INDET pin (default)
1: disable USB-A load insertion detection, then INDET pin functions as a comparator input
*/
#ifndef DIS_INDET
#define DIS_INDET
#endif
#define CTRL0_SET_REG_DIS_INDET                         (0x06)
#define CTRL0_SET_REG_DIS_INDET_WTH                     (0x01)
#define CTRL0_SET_REG_DIS_INDET_FLDSET                  (0x40)
#define CTRL0_SET_REG_DIS_INDET_FLDMSK                  (0xBF)
#define CTRL0_SET_REG_DIS_INDET_ACCESS                  RW

/**
VINREG_RATIO, RW, reset value(0x0)
VINREG setting ratio
0: 100x (default)
1: 40x
Choose 40x ratio when VINREG target value < 10V.
*/
#ifndef VINREG_RATIO
#define VINREG_RATIO
#endif
#define CTRL0_SET_REG_VINREG_RATIO                      (0x04)
#define CTRL0_SET_REG_VINREG_RATIO_WTH                  (0x01)
#define CTRL0_SET_REG_VINREG_RATIO_FLDSET               (0x10)
#define CTRL0_SET_REG_VINREG_RATIO_FLDMSK               (0xEF)
#define CTRL0_SET_REG_VINREG_RATIO_ACCESS               RW

/**
FREQ_SET, RW, reset value(0x1)
Switching frequency setting
00: 150kHz
01: 300kHz (default)
10: Reserved
11: 450kHz
*/
#ifndef FREQ_SET
#define FREQ_SET
#endif
#define CTRL0_SET_REG_FREQ_SET                          (0x02)
#define CTRL0_SET_REG_FREQ_SET_WTH                      (0x02)
#define CTRL0_SET_REG_FREQ_SET_FLDSET                   (0x0C)
#define CTRL0_SET_REG_FREQ_SET_FLDMSK                   (0xF3)
#define CTRL0_SET_REG_FREQ_SET_ACCESS                   RW

/**
DT_SET, RW, reset value(0x0)
Switching dead time setting
00: 20ns (default)
01: 40ns
10: 60ns
11: 80ns
*/
#ifndef DT_SET
#define DT_SET
#endif
#define CTRL0_SET_REG_DT_SET                            (0x00)
#define CTRL0_SET_REG_DT_SET_WTH                        (0x02)
#define CTRL0_SET_REG_DT_SET_FLDSET                     (0x03)
#define CTRL0_SET_REG_DT_SET_FLDMSK                     (0xFC)
#define CTRL0_SET_REG_DT_SET_ACCESS                     RW

#define CTRL0_SET_REG_ACCESS                            RW
#define CTRL0_SET_REG_FIELD_COUNT                       (6)


#define CTRL1_SET_REG                                   (0x0A)

/**
ICHAR_SEL, RW, reset value(0x0)
Charging current selection
0: IBUS as charging current, the trickle charging current and termination current will be based on IBUS (default)
1: IBAT as charging current, the trickle charging current and termination current will be based on IBAT
*/
#ifndef ICHAR_SEL
#define ICHAR_SEL
#endif
#define CTRL1_SET_REG_ICHAR_SEL                         (0x07)
#define CTRL1_SET_REG_ICHAR_SEL_WTH                     (0x01)
#define CTRL1_SET_REG_ICHAR_SEL_FLDSET                  (0x80)
#define CTRL1_SET_REG_ICHAR_SEL_FLDMSK                  (0x7F)
#define CTRL1_SET_REG_ICHAR_SEL_ACCESS                  RW

/**
DIS_TRICKLE, RW, reset value(0x0)
Trickle charge control
0: enable trickle charge phase (default)
1: disable trickle charge phase
*/
#ifndef DIS_TRICKLE
#define DIS_TRICKLE
#endif
#define CTRL1_SET_REG_DIS_TRICKLE                       (0x06)
#define CTRL1_SET_REG_DIS_TRICKLE_WTH                   (0x01)
#define CTRL1_SET_REG_DIS_TRICKLE_FLDSET                (0x40)
#define CTRL1_SET_REG_DIS_TRICKLE_FLDMSK                (0xBF)
#define CTRL1_SET_REG_DIS_TRICKLE_ACCESS                RW

/**
DIS_TERM, RW, reset value(0x0)
Charging termination control
0: enable auto-termination (default)
1: disable auto-termination
*/
#ifndef DIS_TERM
#define DIS_TERM
#endif
#define CTRL1_SET_REG_DIS_TERM                          (0x05)
#define CTRL1_SET_REG_DIS_TERM_WTH                      (0x01)
#define CTRL1_SET_REG_DIS_TERM_FLDSET                   (0x20)
#define CTRL1_SET_REG_DIS_TERM_FLDMSK                   (0xDF)
#define CTRL1_SET_REG_DIS_TERM_ACCESS                   RW

/**
FB_SEL, RW, reset value(0x0)
VBUS voltage setting control, only for discharging mode
0: internal VBUS setting, VBUS output voltage is set by VBUS_RATIO bit and VBUSREF_I_SET bits (default)
1: external VBUS setting, VBUS output voltage is set by resistor divider at FB pin
*/
#ifndef FB_SEL
#define FB_SEL
#endif
#define CTRL1_SET_REG_FB_SEL                            (0x04)
#define CTRL1_SET_REG_FB_SEL_WTH                        (0x01)
#define CTRL1_SET_REG_FB_SEL_FLDSET                     (0x10)
#define CTRL1_SET_REG_FB_SEL_FLDMSK                     (0xEF)
#define CTRL1_SET_REG_FB_SEL_ACCESS                     RW

/**
TRICKLE_SET, RW, reset value(0x0)
Trickle charge phase threshold setting
0: 70% of VBAT voltage setting (default)
1: 60% of VBAT voltage setting
*/
#ifndef TRICKLE_SET
#define TRICKLE_SET
#endif
#define CTRL1_SET_REG_TRICKLE_SET                       (0x03)
#define CTRL1_SET_REG_TRICKLE_SET_WTH                   (0x01)
#define CTRL1_SET_REG_TRICKLE_SET_FLDSET                (0x08)
#define CTRL1_SET_REG_TRICKLE_SET_FLDMSK                (0xF7)
#define CTRL1_SET_REG_TRICKLE_SET_ACCESS                RW

/**
DIS_OVP, RW, reset value(0x0)
OVP protection setting for discharging mode
0: enable OVP protection (default)
1: disable OVP protection
*/
#ifndef DIS_OVP
#define DIS_OVP
#endif
#define CTRL1_SET_REG_DIS_OVP                           (0x02)
#define CTRL1_SET_REG_DIS_OVP_WTH                       (0x01)
#define CTRL1_SET_REG_DIS_OVP_FLDSET                    (0x04)
#define CTRL1_SET_REG_DIS_OVP_FLDMSK                    (0xFB)
#define CTRL1_SET_REG_DIS_OVP_ACCESS                    RW

/**
ICOM_SET, RW, reset value(0x0)
*/
#ifndef ICOM_SET
#define ICOM_SET
#endif
#define CTRL1_SET_REG_ICOM_SET                          (0x00)
#define CTRL1_SET_REG_ICOM_SET_WTH                      (0x01)
#define CTRL1_SET_REG_ICOM_SET_FLDSET                   (0x01)
#define CTRL1_SET_REG_ICOM_SET_FLDMSK                   (0xFE)
#define CTRL1_SET_REG_ICOM_SET_ACCESS                   RW

#define CTRL1_SET_REG_ACCESS                            RW
#define CTRL1_SET_REG_FIELD_COUNT                       (8)


#define CTRL2_SET_REG                                   (0x0B)

/**
SOFTSTART_SET, RW, reset value(0x0)
Soft start slew rate setting
00: 0.0625mV/μs (default)
01: 0.125mV/μs
10: 0.25mV/μs
11: 0.5mV/μs
*/
#ifndef SOFTSTART_SET
#define SOFTSTART_SET
#endif
#define CTRL2_SET_REG_SOFTSTART_SET                     (0x04)
#define CTRL2_SET_REG_SOFTSTART_SET_WTH                 (0x02)
#define CTRL2_SET_REG_SOFTSTART_SET_FLDSET              (0x30)
#define CTRL2_SET_REG_SOFTSTART_SET_FLDMSK              (0xCF)
#define CTRL2_SET_REG_SOFTSTART_SET_ACCESS              RW

/**
FACTORY, RW, reset value(0x0)
Factory setting bit. MCU shall write this bit to 1 after power up.
*/
#ifndef FACTORY
#define FACTORY
#endif
#define CTRL2_SET_REG_FACTORY                          (0x03)
#define CTRL2_SET_REG_FACTORY_WTH                      (0x01)
#define CTRL2_SET_REG_FACTORY_FLDSET                   (0x08)
#define CTRL2_SET_REG_FACTORY_FLDMSK                   (0xF7)
#define CTRL2_SET_REG_FACTORY_ACCESS                   RW

/**
EN_DITHER, RW, reset value(0x0)
Enable switching frequency dithering function at PGATE pin:
0: disable frequency dithering function, PGATE pin used as PMOS gate control (default)
1: enable frequency dithering function, PGATE pin used to set the frequency dithering
*/
#ifndef EN_DITHER
#define EN_DITHER
#endif
#define CTRL2_SET_REG_EN_DITHER                         (0x02)
#define CTRL2_SET_REG_EN_DITHER_WTH                     (0x01)
#define CTRL2_SET_REG_EN_DITHER_FLDSET                  (0x04)
#define CTRL2_SET_REG_EN_DITHER_FLDMSK                  (0xFB)
#define CTRL2_SET_REG_EN_DITHER_ACCESS                  RW

/**
SLEW_SET, RW, reset value(0x1)
Slew rate setting for VBUS dynamic change in discharging mode
00: 1mV/μs
01: 2mV/μs (default)
10: 4mV/μs
11: 8mV/μs
*/
#ifndef SLEW_SET
#define SLEW_SET
#endif
#define CTRL2_SET_REG_SLEW_SET                          (0x00)
#define CTRL2_SET_REG_SLEW_SET_WTH                      (0x02)
#define CTRL2_SET_REG_SLEW_SET_FLDSET                   (0x03)
#define CTRL2_SET_REG_SLEW_SET_FLDMSK                   (0xFC)
#define CTRL2_SET_REG_SLEW_SET_ACCESS                   RW

#define CTRL2_SET_REG_ACCESS                            RW
#define CTRL2_SET_REG_FIELD_COUNT                       (5)


#define CTRL3_SET_REG                                   (0x0C)

/**
EN_PGATE, RW, reset value(0x0)
PGATE control
0: PGATE outputs logic high to turn off PMOS (default)
1: PGATE outputs logic low to turn on PMOS
*/
#ifndef EN_PGATE
#define EN_PGATE
#endif
#define CTRL3_SET_REG_EN_PGATE                          (0x07)
#define CTRL3_SET_REG_EN_PGATE_WTH                      (0x01)
#define CTRL3_SET_REG_EN_PGATE_FLDSET                   (0x80)
#define CTRL3_SET_REG_EN_PGATE_FLDMSK                   (0x7F)
#define CTRL3_SET_REG_EN_PGATE_ACCESS                   RW

/**
GPO_CTRL, RW, reset value(0x0)
GPO output control
0: Open drain output (default)
1: Logic low output
*/
#ifndef GPO_CTRL
#define GPO_CTRL
#endif
#define CTRL3_SET_REG_GPO_CTRL                          (0x06)
#define CTRL3_SET_REG_GPO_CTRL_WTH                      (0x01)
#define CTRL3_SET_REG_GPO_CTRL_FLDSET                   (0x40)
#define CTRL3_SET_REG_GPO_CTRL_FLDMSK                   (0xBF)
#define CTRL3_SET_REG_GPO_CTRL_ACCESS                   RW

/**
AD_START, RW, reset value(0x0)
ADC control
0: stop ADC conversion (default)
1: start ADC conversion, MCU can read the voltage/current values from ADC registers
*/
#ifndef AD_START
#define AD_START
#endif
#define CTRL3_SET_REG_AD_START                          (0x05)
#define CTRL3_SET_REG_AD_START_WTH                      (0x01)
#define CTRL3_SET_REG_AD_START_FLDSET                   (0x20)
#define CTRL3_SET_REG_AD_START_FLDMSK                   (0xDF)
#define CTRL3_SET_REG_AD_START_ACCESS                   RW

/**
ILIM_BW_SEL, RW, reset value(0x0)
ILIM loop bandwidth setting:
0: 5kHz (default)
1: 1.25kHz
*/
#ifndef ILIM_BW_SEL
#define ILIM_BW_SEL
#endif
#define CTRL3_SET_REG_ILIM_BW_SEL                       (0x04)
#define CTRL3_SET_REG_ILIM_BW_SEL_WTH                   (0x01)
#define CTRL3_SET_REG_ILIM_BW_SEL_FLDSET                (0x10)
#define CTRL3_SET_REG_ILIM_BW_SEL_FLDMSK                (0xEF)
#define CTRL3_SET_REG_ILIM_BW_SEL_ACCESS                RW

/**
LOOP_SET, RW, reset value(0x0)
Loop response control
0: Normal loop response (default)
1: Improve the loop response
*/
#ifndef LOOP_SET
#define LOOP_SET
#endif
#define CTRL3_SET_REG_LOOP_SET                          (0x03)
#define CTRL3_SET_REG_LOOP_SET_WTH                      (0x01)
#define CTRL3_SET_REG_LOOP_SET_FLDSET                   (0x08)
#define CTRL3_SET_REG_LOOP_SET_FLDMSK                   (0xF7)
#define CTRL3_SET_REG_LOOP_SET_ACCESS                   RW

/**
DIS_SHORTFOLDBACK, RW, reset value(0x0)
IBUS current foldback control for VBUS short circuit condition, only valid in discharging mode
0: IBUS is fold-back to 1/10 of IBUS_LIM setting (default)
1: disable fold-back.
*/
#ifndef DIS_SHORTFOLDBACK
#define DIS_SHORTFOLDBACK
#endif
#define CTRL3_SET_REG_DIS_SHORTFOLDBACK                 (0x02)
#define CTRL3_SET_REG_DIS_SHORTFOLDBACK_WTH             (0x01)
#define CTRL3_SET_REG_DIS_SHORTFOLDBACK_FLDSET          (0x04)
#define CTRL3_SET_REG_DIS_SHORTFOLDBACK_FLDMSK          (0xFB)
#define CTRL3_SET_REG_DIS_SHORTFOLDBACK_ACCESS          RW

/**
EOC_SET, RW, reset value(0x1)
Current threshold setting for End Of Charging (EOC) detection
0: 1/25 of charging current
1: 1/10 of charging current (default)
1/25 option is not recommended for ≤ 2A ILIMx setting.
*/
#ifndef EOC_SET
#define EOC_SET
#endif
#define CTRL3_SET_REG_EOC_SET                           (0x01)
#define CTRL3_SET_REG_EOC_SET_WTH                       (0x01)
#define CTRL3_SET_REG_EOC_SET_FLDSET                    (0x02)
#define CTRL3_SET_REG_EOC_SET_FLDMSK                    (0xFD)
#define CTRL3_SET_REG_EOC_SET_ACCESS                    RW

/**
EN_PFM, RW, reset value(0x0)
PFM control under light load condition, only for discharging mode
0: disable PFM mode (PWM mode enabled) (default)
1: enable PFM mode
*/
#ifndef EN_PFM
#define EN_PFM
#endif
#define CTRL3_SET_REG_EN_PFM                            (0x00)
#define CTRL3_SET_REG_EN_PFM_WTH                        (0x01)
#define CTRL3_SET_REG_EN_PFM_FLDSET                     (0x01)
#define CTRL3_SET_REG_EN_PFM_FLDMSK                     (0xFE)
#define CTRL3_SET_REG_EN_PFM_ACCESS                     RW

#define CTRL3_SET_REG_ACCESS                            RW
#define CTRL3_SET_REG_FIELD_COUNT                       (8)


#define VBUS_FB_VALUE_REG                               (0x0D)

/**
VBUS_FB_VALUE, RO, reset value(0x0)
The highest 8-bit of the ADC reading of VBUS voltage (total 10-bit).
VBUS voltage is calculated as
VBUS = (4 x VBUS_FB_VALUE + VBUS_FB_VALUE2 + 1) x VBUS_RATIO x 2 mV
VBUS_FB_VALUE range: 0 ~ 255
0000 0000: 0
0000 0001: 1
0000 0010: 2
….
1111 1111: 255
*/
#ifndef VBUS_FB_VALUE
#define VBUS_FB_VALUE
#endif
#define VBUS_FB_VALUE_REG_VBUS_FB_VALUE                 (0x00)
#define VBUS_FB_VALUE_REG_VBUS_FB_VALUE_WTH             (0x08)
#define VBUS_FB_VALUE_REG_VBUS_FB_VALUE_FLDSET          (0xFF)
#define VBUS_FB_VALUE_REG_VBUS_FB_VALUE_FLDMSK          (0x00)
#define VBUS_FB_VALUE_REG_VBUS_FB_VALUE_ACCESS          RO

#define VBUS_FB_VALUE_REG_ACCESS                        RO
#define VBUS_FB_VALUE_REG_FIELD_COUNT                   (1)


#define VBUS_FB_VALUE2_REG                              (0x0E)

/**
VBUS_FB_VALUE2, RO, reset value(0x0)
The lowest 2-bit of the ADC reading of VBUS voltage (total 10-bit).
VBUS voltage is calculated as VBUS voltage is calculated as
VBUS = (4 x VBUS_FB_VALUE + VBUS_FB_VALUE2 + 1) x VBUS_RATIO x 2 mV
VBUS_FB_VALUE2 range: 0 ~ 3
00: 0
01: 1
10: 2
11: 3
*/
#ifndef VBUS_FB_VALUE2
#define VBUS_FB_VALUE2
#endif
#define VBUS_FB_VALUE2_REG_VBUS_FB_VALUE2               (0x06)
#define VBUS_FB_VALUE2_REG_VBUS_FB_VALUE2_WTH           (0x02)
#define VBUS_FB_VALUE2_REG_VBUS_FB_VALUE2_FLDSET        (0xC0)
#define VBUS_FB_VALUE2_REG_VBUS_FB_VALUE2_FLDMSK        (0x3F)
#define VBUS_FB_VALUE2_REG_VBUS_FB_VALUE2_ACCESS        RO

#define VBUS_FB_VALUE2_REG_ACCESS                       RO
#define VBUS_FB_VALUE2_REG_FIELD_COUNT                  (2)


#define VBAT_FB_VALUE_REG                               (0x0F)

/**
VBAT_VALUE, RO, reset value(0x0)
The highest 8-bit of the ADC reading of VBAT voltage (total 10-bit).
VBAT voltage is calculated as
VBAT = (4 x VBAT_FB_VALUE + VBAT_FB_VALUE2 + 1) x VBAT_MON_RATIO x 2 mV
VBAT_FB_VALUE range: 0 ~ 255
0000 0000: 0
0000 0001: 1
0000 0010: 2
….
1111 1111: 255
*/
#ifndef VBAT_VALUE
#define VBAT_VALUE
#endif
#define VBAT_FB_VALUE_REG_VBAT_VALUE                    (0x00)
#define VBAT_FB_VALUE_REG_VBAT_VALUE_WTH                (0x08)
#define VBAT_FB_VALUE_REG_VBAT_VALUE_FLDSET             (0xFF)
#define VBAT_FB_VALUE_REG_VBAT_VALUE_FLDMSK             (0x00)
#define VBAT_FB_VALUE_REG_VBAT_VALUE_ACCESS             RO

#define VBAT_FB_VALUE_REG_ACCESS                        RO
#define VBAT_FB_VALUE_REG_FIELD_COUNT                   (1)


#define VBAT_FB_VALUE2_REG                              (0x10)

/**
VBAT_FB_VALUE_2, RO, reset value(0x0)
The lowest 2-bit of the ADC reading of VBAT voltage (total 10-bit).
VBAT voltage is calculated as
VBAT = (4 x VBAT_FB_VALUE + VBAT_FB_VALUE2 + 1) x VBAT_MON_RATIO x 2 mV
VBAT_FB_VALUE_2 range: 0 ~ 3
00: 0
01: 1
10: 2
11: 3
*/
#ifndef VBAT_FB_VALUE_2
#define VBAT_FB_VALUE_2
#endif
#define VBAT_FB_VALUE2_REG_VBAT_FB_VALUE_2              (0x06)
#define VBAT_FB_VALUE2_REG_VBAT_FB_VALUE_2_WTH          (0x02)
#define VBAT_FB_VALUE2_REG_VBAT_FB_VALUE_2_FLDSET       (0xC0)
#define VBAT_FB_VALUE2_REG_VBAT_FB_VALUE_2_FLDMSK       (0x3F)
#define VBAT_FB_VALUE2_REG_VBAT_FB_VALUE_2_ACCESS       RO

#define VBAT_FB_VALUE2_REG_ACCESS                       RO
#define VBAT_FB_VALUE2_REG_FIELD_COUNT                  (2)


#define IBUS_VALUE_REG                                  (0x11)

/**
IBUS_VALUE, RO, reset value(0x0)
The highest 8-bit of the ADC reading of IBUS current (total 10-bit).
IBUS current is calculated as IBUS (A) = (4 x IBUS_VALUE + IBUS_VALUE2 + 1)×21200 × IBUS_RATIO ×10 mΩRS1
IBUS_VALUE range: 0 ~ 255
0000 0000: 0
0000 0001: 1
0000 0010: 2
….
1111 1111: 255
*/
#ifndef IBUS_VALUE
#define IBUS_VALUE
#endif
#define IBUS_VALUE_REG_IBUS_VALUE                       (0x00)
#define IBUS_VALUE_REG_IBUS_VALUE_WTH                   (0x08)
#define IBUS_VALUE_REG_IBUS_VALUE_FLDSET                (0xFF)
#define IBUS_VALUE_REG_IBUS_VALUE_FLDMSK                (0x00)
#define IBUS_VALUE_REG_IBUS_VALUE_ACCESS                RO

#define IBUS_VALUE_REG_ACCESS                           RO
#define IBUS_VALUE_REG_FIELD_COUNT                      (1)


#define IBUS_VALUE2_REG                                 (0x12)

/**
IBUS_VALUE2, RO, reset value(0x0)
The lowest 2-bit of the ADC reading of IBUS current (total 10-bit).
IBUS current is calculated as IBUS (A) = (4 x IBUS_VALUE + IBUS_VALUE2 + 1)×21200 × IBUS_RATIO ×10 mΩRS1
IBUS_VALUE2 range: 0 ~ 3
00: 0
01: 1
10: 2
11: 3
*/
#ifndef IBUS_VALUE2
#define IBUS_VALUE2
#endif
#define IBUS_VALUE2_REG_IBUS_VALUE2                     (0x06)
#define IBUS_VALUE2_REG_IBUS_VALUE2_WTH                 (0x02)
#define IBUS_VALUE2_REG_IBUS_VALUE2_FLDSET              (0xC0)
#define IBUS_VALUE2_REG_IBUS_VALUE2_FLDMSK              (0x3F)
#define IBUS_VALUE2_REG_IBUS_VALUE2_ACCESS              RO

#define IBUS_VALUE2_REG_ACCESS                          RO
#define IBUS_VALUE2_REG_FIELD_COUNT                     (2)


#define IBAT_VALUE_REG                                  (0x13)

/**
IBAT_VALUE, RO, reset value(0x0)
The highest 8-bit of the ADC reading of IBAT current (total 10-bit).
IBAT current is calculated as IBAT (A) = (4 x IBAT_VALUE + IBAT_VALUE2 + 1)×21200 × IBAT_RATIO ×10 mΩRS2
IBAT_VALUE range: 0 ~ 255
0000 0000: 0
0000 0001: 1
0000 0010: 2
….
1111 1111: 255
*/
#ifndef IBAT_VALUE
#define IBAT_VALUE
#endif
#define IBAT_VALUE_REG_IBAT_VALUE                       (0x00)
#define IBAT_VALUE_REG_IBAT_VALUE_WTH                   (0x08)
#define IBAT_VALUE_REG_IBAT_VALUE_FLDSET                (0xFF)
#define IBAT_VALUE_REG_IBAT_VALUE_FLDMSK                (0x00)
#define IBAT_VALUE_REG_IBAT_VALUE_ACCESS                RO

#define IBAT_VALUE_REG_ACCESS                           RO
#define IBAT_VALUE_REG_FIELD_COUNT                      (1)


#define IBAT_VALUE2_REG                                 (0x14)

/**
IBAT_VALUE2, RO, reset value(0x0)
The lowest 2-bit of the ADC reading of IBAT current (total 10-bit).
IBAT current is calculated as IBAT (A) = (4 x IBAT_VALUE + IBAT_VALUE2 + 1)×21200 × IBAT_RATIO ×10 mΩRS2
IBAT_VALUE2 range: 0 ~ 3
00: 0
01: 1
10: 2
11: 3
*/
#ifndef IBAT_VALUE2
#define IBAT_VALUE2
#endif
#define IBAT_VALUE2_REG_IBAT_VALUE2                     (0x06)
#define IBAT_VALUE2_REG_IBAT_VALUE2_WTH                 (0x02)
#define IBAT_VALUE2_REG_IBAT_VALUE2_FLDSET              (0xC0)
#define IBAT_VALUE2_REG_IBAT_VALUE2_FLDMSK              (0x3F)
#define IBAT_VALUE2_REG_IBAT_VALUE2_ACCESS              RO

#define IBAT_VALUE2_REG_ACCESS                          RO
#define IBAT_VALUE2_REG_FIELD_COUNT                     (2)


#define ADIN_VALUE_REG                                  (0x15)

/**
ADIN_VALUE, RO, reset value(0x0)
The highest 8-bit of the ADC reading of ADIN voltage (total 10-bit).
ADIN voltage is calculated as
VADIN = (4 x ADIN_VALUE + ADIN_VALUE2 + 1) x 2 mV
ADIN_VALUE range: 0 ~ 255
0000 0000: 0
0000 0001: 1
0000 0010: 2
….
1111 1111: 255
*/
#ifndef ADIN_VALUE
#define ADIN_VALUE
#endif
#define ADIN_VALUE_REG_ADIN_VALUE                       (0x00)
#define ADIN_VALUE_REG_ADIN_VALUE_WTH                   (0x08)
#define ADIN_VALUE_REG_ADIN_VALUE_FLDSET                (0xFF)
#define ADIN_VALUE_REG_ADIN_VALUE_FLDMSK                (0x00)
#define ADIN_VALUE_REG_ADIN_VALUE_ACCESS                RO

#define ADIN_VALUE_REG_ACCESS                           RO
#define ADIN_VALUE_REG_FIELD_COUNT                      (1)


#define ADIN_VALUE_2_REG                                (0x16)

/**
ADIN_VALUE2, RO, reset value(0x0)
The lowest 2-bit of the ADC reading of ADIN voltage (total 10-bit).
ADIN voltage is calculated as
VADIN = (4 x ADIN_VALUE + ADIN_VALUE2 + 1) x 2 mV
ADIN_VALUE_2 range: 0 ~ 3
00: 0
01: 1
10: 2
11: 3
*/
#ifndef ADIN_VALUE2
#define ADIN_VALUE2
#endif
#define ADIN_VALUE_2_REG_ADIN_VALUE2                    (0x06)
#define ADIN_VALUE_2_REG_ADIN_VALUE2_WTH                (0x02)
#define ADIN_VALUE_2_REG_ADIN_VALUE2_FLDSET             (0xC0)
#define ADIN_VALUE_2_REG_ADIN_VALUE2_FLDMSK             (0x3F)
#define ADIN_VALUE_2_REG_ADIN_VALUE2_ACCESS             RO

#define ADIN_VALUE_2_REG_ACCESS                         RO
#define ADIN_VALUE_2_REG_FIELD_COUNT                    (2)


#define STATUS_REG                                      (0x17)

/**
AC_OK, RO, reset value(0x0)
1: AC adapter is inserted
*/
#ifndef AC_OK
#define AC_OK
#endif
#define STATUS_REG_AC_OK                                (0x06)
#define STATUS_REG_AC_OK_WTH                            (0x01)
#define STATUS_REG_AC_OK_FLDSET                         (0x40)
#define STATUS_REG_AC_OK_FLDMSK                         (0xBF)
#define STATUS_REG_AC_OK_ACCESS                         RO

/**
INDET2, RO, reset value(0x0)
if DIS_INDET = 0:
1: USB-A load insert is detected at INDET2 pin
if DIS_INDET = 1:
1: INDET pin voltage is higher than 1V (when PSTOP is low) or 0.7V (when PSTOP is high)
*/
#ifndef INDET2
#define INDET2
#endif
#define STATUS_REG_INDET2                               (0x05)
#define STATUS_REG_INDET2_WTH                           (0x01)
#define STATUS_REG_INDET2_FLDSET                        (0x20)
#define STATUS_REG_INDET2_FLDMSK                        (0xDF)
#define STATUS_REG_INDET2_ACCESS                        RO

/**
INDET1, RO, reset value(0x0)
if DIS_INDET = 0:
1: USB-A load insert is detected at INDET pin
if DIS_INDET = 1:
1: INDET pin voltage is higher than 1V (when PSTOP is low) or 0.7V (when PSTOP is high)
*/
#ifndef INDET1
#define INDET1
#endif
#define STATUS_REG_INDET1                               (0x04)
#define STATUS_REG_INDET1_WTH                           (0x01)
#define STATUS_REG_INDET1_FLDSET                        (0x10)
#define STATUS_REG_INDET1_FLDMSK                        (0xEF)
#define STATUS_REG_INDET1_ACCESS                        RO

/**
VBUS_SHORT, RO, reset value(0x0)
1: VBUS short circuit fault happens in discharging mode
*/
#ifndef VBUS_SHORT
#define VBUS_SHORT
#endif
#define STATUS_REG_VBUS_SHORT                           (0x03)
#define STATUS_REG_VBUS_SHORT_WTH                       (0x01)
#define STATUS_REG_VBUS_SHORT_FLDSET                    (0x08)
#define STATUS_REG_VBUS_SHORT_FLDMSK                    (0xF7)
#define STATUS_REG_VBUS_SHORT_ACCESS                    RO

/**
OTP, RO, reset value(0x0)
1: OTP fault happens
*/
#ifndef OTP
#define OTP
#endif
#define STATUS_REG_OTP                                  (0x02)
#define STATUS_REG_OTP_WTH                              (0x01)
#define STATUS_REG_OTP_FLDSET                           (0x04)
#define STATUS_REG_OTP_FLDMSK                           (0xFB)
#define STATUS_REG_OTP_ACCESS                           RO

/**
EOC, RO, reset value(0x0)
1: EOC conditions are satisfied
*/
#ifndef EOC
#define EOC
#endif
#define STATUS_REG_EOC                                  (0x01)
#define STATUS_REG_EOC_WTH                              (0x01)
#define STATUS_REG_EOC_FLDSET                           (0x02)
#define STATUS_REG_EOC_FLDMSK                           (0xFD)
#define STATUS_REG_EOC_ACCESS                           RO

/**
ICOM, RO, reset value(0x0)
1: Small current is detected (IBUS < ICOM_SET) in discharging mode
*/
#ifndef ICOM
#define ICOM
#endif
#define STATUS_REG_ICOM                                 (0x00)
#define STATUS_REG_ICOM_WTH                             (0x01)
#define STATUS_REG_ICOM_FLDSET                          (0x01)
#define STATUS_REG_ICOM_FLDMSK                          (0xFE)
#define STATUS_REG_ICOM_ACCESS                          RO

#define STATUS_REG_ACCESS                               RO
#define STATUS_REG_FIELD_COUNT                          (8)


#define RSVED01_REG                                     (0x18)

#define RSVED01_REG_ACCESS                              RO
#define RSVED01_REG_FIELD_COUNT                         (1)


#define MASK_REG                                        (0x19)

/**
AC_OK_MASK, RW, reset value(0x0)
1: Interrupt is disabled
*/
#ifndef AC_OK_MASK
#define AC_OK_MASK
#endif
#define MASK_REG_AC_OK_FLDSET                           (0x06)
#define MASK_REG_AC_OK_MASK_WTH                         (0x01)
#define MASK_REG_AC_OK_MASK_FLDSET                      (0x40)
#define MASK_REG_AC_OK_MASK_FLDMSK                      (0xBF)
#define MASK_REG_AC_OK_MASK_ACCESS                      RW

/**
NDET_MASK, RW, reset value(0x0)
1: Interrupt is disabled
*/
#ifndef NDET_MASK
#define NDET_MASK
#endif
#define MASK_REG_NDET_FLDSET                            (0x05)
#define MASK_REG_NDET_MASK_WTH                          (0x01)
#define MASK_REG_NDET_MASK_FLDSET                       (0x20)
#define MASK_REG_NDET_MASK_FLDMSK                       (0xDF)
#define MASK_REG_NDET_MASK_ACCESS                       RW

/**
VBUS_SHORT_MASK, RW, reset value(0x0)
1: Interrupt is disabled
*/
#ifndef VBUS_SHORT_MASK
#define VBUS_SHORT_MASK
#endif
#define MASK_REG_VBUS_SHORT_FLDSET                      (0x03)
#define MASK_REG_VBUS_SHORT_MASK_WTH                    (0x01)
#define MASK_REG_VBUS_SHORT_MASK_FLDSET                 (0x08)
#define MASK_REG_VBUS_SHORT_MASK_FLDMSK                 (0xF7)
#define MASK_REG_VBUS_SHORT_MASK_ACCESS                 RW

/**
OTP_MASK, RW, reset value(0x0)
1: Interrupt is disabled
*/
#ifndef OTP_MASK
#define OTP_MASK
#endif
#define MASK_REG_OTP_FLDSET                             (0x02)
#define MASK_REG_OTP_MASK_WTH                           (0x01)
#define MASK_REG_OTP_MASK_FLDSET                        (0x04)
#define MASK_REG_OTP_MASK_FLDMSK                        (0xFB)
#define MASK_REG_OTP_MASK_ACCESS                        RW

/**
EOC_MASK, RW, reset value(0x0)
1: Interrupt is disabled
*/
#ifndef EOC_MASK
#define EOC_MASK
#endif
#define MASK_REG_EOC_FLDSET                             (0x01)
#define MASK_REG_EOC_MASK_WTH                           (0x01)
#define MASK_REG_EOC_MASK_FLDSET                        (0x02)
#define MASK_REG_EOC_MASK_FLDMSK                        (0xFD)
#define MASK_REG_EOC_MASK_ACCESS                        RW

/**
ICOM_MASK, RW, reset value(0x0)
1: Interrupt is disabled
*/
#ifndef ICOM_MASK
#define ICOM_MASK
#endif
#define MASK_REG_ICOM_FLDSET                            (0x00)
#define MASK_REG_ICOM_MASK_WTH                          (0x01)
#define MASK_REG_ICOM_MASK_FLDSET                       (0x01)
#define MASK_REG_ICOM_MASK_FLDMSK                       (0xFE)
#define MASK_REG_ICOM_MASK_ACCESS                       RW

#define MASK_REG_ACCESS                                 RW
#define MASK_REG_FIELD_COUNT                            (8)


#define RSVED02_REG                                     (0x1A)

#define RSVED02_REG_ACCESS                              RO
#define RSVED02_REG_FIELD_COUNT                         (1)


#define RSVED03_REG                                     (0x1B)

#define RSVED03_REG_ACCESS                              RO
#define RSVED03_REG_FIELD_COUNT                         (1)



#endif /* #ifndef __SC8812_REG_DEFS_H_ */

