/**
 * \file    reg_def_pwm.h
 * \brief   Register definition file
 * 
 * \par     Copyright (c) 2019 UWE Technologies Corp., Ltd. All Rights Reserved.
 * \author  James
 * \date    2019-04-26
 * \version 
 * 
 * \history 
 *  Date        Note
 *  2019-04-26  Original Creation
 * 
 */

#ifndef __REG_DEF_PWM_H_
#define __REG_DEF_PWM_H_



#define PWM_EN_REG                                      (0x40000900)

/**
PWM_EN, RW, reset value(0x0)
PWM channels enable, high active
*/
#ifndef PWM_EN
#define PWM_EN
#endif
#define PWM_EN_REG_PWM_EN                               (0x00)
#define PWM_EN_REG_PWM_EN_WTH                           (0x06)
#define PWM_EN_REG_PWM_EN_FLDSET                        (0x0000003F)
#define PWM_EN_REG_PWM_EN_FLDMSK                        (0xFFFFFFC0)


#define PWM0_CFG_REG_0                                  (0x40000904)

/**
PWM_INIT_VAL, RW, reset value(0x0)
PWM waveform initial value, 1'b1 : PWM waveform start as high; 1'b0 : PWM waveform start as low.
*/
#ifndef PWM_INIT_VAL
#define PWM_INIT_VAL
#endif
#define PWM0_CFG_REG_0_PWM_INIT_VAL                     (0x1F)
#define PWM0_CFG_REG_0_PWM_INIT_VAL_WTH                 (0x01)
#define PWM0_CFG_REG_0_PWM_INIT_VAL_FLDSET              (0x80000000)
#define PWM0_CFG_REG_0_PWM_INIT_VAL_FLDMSK              (0x7FFFFFFF)

/**
PWM_PER, RW, reset value(0x0)
PWM waveform period 
*/
#ifndef PWM_PER
#define PWM_PER
#endif
#define PWM0_CFG_REG_0_PWM_PER                          (0x00)
#define PWM0_CFG_REG_0_PWM_PER_WTH                      (0x10)
#define PWM0_CFG_REG_0_PWM_PER_FLDSET                   (0x0000FFFF)
#define PWM0_CFG_REG_0_PWM_PER_FLDMSK                   (0xFFFF0000)


#define PWM0_CFG_REG_1                                  (0x40000908)

/**
PWM_CMP_1, RW, reset value(0x0)
PWM counter compare point 1, when counter equal to this compare point value, the output is toggled
*/
#ifndef PWM_CMP_1
#define PWM_CMP_1
#endif
#define PWM0_CFG_REG_1_PWM_CMP_1                        (0x10)
#define PWM0_CFG_REG_1_PWM_CMP_1_WTH                    (0x10)
#define PWM0_CFG_REG_1_PWM_CMP_1_FLDSET                 (0xFFFF0000)
#define PWM0_CFG_REG_1_PWM_CMP_1_FLDMSK                 (0x0000FFFF)

/**
PWM_CMP_2, RW, reset value(0x0)
PWM counter compare point 2, when counter equal to this compare point value, the output is toggled
*/
#ifndef PWM_CMP_2
#define PWM_CMP_2
#endif
#define PWM0_CFG_REG_1_PWM_CMP_2                        (0x00)
#define PWM0_CFG_REG_1_PWM_CMP_2_WTH                    (0x10)
#define PWM0_CFG_REG_1_PWM_CMP_2_FLDSET                 (0x0000FFFF)
#define PWM0_CFG_REG_1_PWM_CMP_2_FLDMSK                 (0xFFFF0000)


#define PWM1_CFG_REG_0                                  (0x4000090C)

/**
PWM_INIT_VAL, RW, reset value(0x0)
PWM waveform initial value, 1'b1 : PWM waveform start as high; 1'b0 : PWM waveform start as low.
*/
#ifndef PWM_INIT_VAL
#define PWM_INIT_VAL
#endif
#define PWM1_CFG_REG_0_PWM_INIT_VAL                     (0x1F)
#define PWM1_CFG_REG_0_PWM_INIT_VAL_WTH                 (0x01)
#define PWM1_CFG_REG_0_PWM_INIT_VAL_FLDSET              (0x80000000)
#define PWM1_CFG_REG_0_PWM_INIT_VAL_FLDMSK              (0x7FFFFFFF)

/**
PWM_PER, RW, reset value(0x0)
PWM waveform period 
*/
#ifndef PWM_PER
#define PWM_PER
#endif
#define PWM1_CFG_REG_0_PWM_PER                          (0x00)
#define PWM1_CFG_REG_0_PWM_PER_WTH                      (0x10)
#define PWM1_CFG_REG_0_PWM_PER_FLDSET                   (0x0000FFFF)
#define PWM1_CFG_REG_0_PWM_PER_FLDMSK                   (0xFFFF0000)


#define PWM1_CFG_REG_1                                  (0x40000910)

/**
PWM_CMP_1, RW, reset value(0x0)
PWM counter compare point 1, when counter equal to this compare point value, the output is toggled
*/
#ifndef PWM_CMP_1
#define PWM_CMP_1
#endif
#define PWM1_CFG_REG_1_PWM_CMP_1                        (0x10)
#define PWM1_CFG_REG_1_PWM_CMP_1_WTH                    (0x10)
#define PWM1_CFG_REG_1_PWM_CMP_1_FLDSET                 (0xFFFF0000)
#define PWM1_CFG_REG_1_PWM_CMP_1_FLDMSK                 (0x0000FFFF)

/**
PWM_CMP_2, RW, reset value(0x0)
PWM counter compare point 2, when counter equal to this compare point value, the output is toggled
*/
#ifndef PWM_CMP_2
#define PWM_CMP_2
#endif
#define PWM1_CFG_REG_1_PWM_CMP_2                        (0x00)
#define PWM1_CFG_REG_1_PWM_CMP_2_WTH                    (0x10)
#define PWM1_CFG_REG_1_PWM_CMP_2_FLDSET                 (0x0000FFFF)
#define PWM1_CFG_REG_1_PWM_CMP_2_FLDMSK                 (0xFFFF0000)


#define PWM2_CFG_REG_0                                  (0x40000914)

/**
PWM_INIT_VAL, RW, reset value(0x0)
PWM waveform initial value, 1'b1 : PWM waveform start as high; 1'b0 : PWM waveform start as low.
*/
#ifndef PWM_INIT_VAL
#define PWM_INIT_VAL
#endif
#define PWM2_CFG_REG_0_PWM_INIT_VAL                     (0x1F)
#define PWM2_CFG_REG_0_PWM_INIT_VAL_WTH                 (0x01)
#define PWM2_CFG_REG_0_PWM_INIT_VAL_FLDSET              (0x80000000)
#define PWM2_CFG_REG_0_PWM_INIT_VAL_FLDMSK              (0x7FFFFFFF)

/**
PWM_PER, RW, reset value(0x0)
PWM waveform period 
*/
#ifndef PWM_PER
#define PWM_PER
#endif
#define PWM2_CFG_REG_0_PWM_PER                          (0x00)
#define PWM2_CFG_REG_0_PWM_PER_WTH                      (0x10)
#define PWM2_CFG_REG_0_PWM_PER_FLDSET                   (0x0000FFFF)
#define PWM2_CFG_REG_0_PWM_PER_FLDMSK                   (0xFFFF0000)


#define PWM2_CFG_REG_1                                  (0x40000918)

/**
PWM_CMP_1, RW, reset value(0x0)
PWM counter compare point 1, when counter equal to this compare point value, the output is toggled
*/
#ifndef PWM_CMP_1
#define PWM_CMP_1
#endif
#define PWM2_CFG_REG_1_PWM_CMP_1                        (0x10)
#define PWM2_CFG_REG_1_PWM_CMP_1_WTH                    (0x10)
#define PWM2_CFG_REG_1_PWM_CMP_1_FLDSET                 (0xFFFF0000)
#define PWM2_CFG_REG_1_PWM_CMP_1_FLDMSK                 (0x0000FFFF)

/**
PWM_CMP_2, RW, reset value(0x0)
PWM counter compare point 2, when counter equal to this compare point value, the output is toggled
*/
#ifndef PWM_CMP_2
#define PWM_CMP_2
#endif
#define PWM2_CFG_REG_1_PWM_CMP_2                        (0x00)
#define PWM2_CFG_REG_1_PWM_CMP_2_WTH                    (0x10)
#define PWM2_CFG_REG_1_PWM_CMP_2_FLDSET                 (0x0000FFFF)
#define PWM2_CFG_REG_1_PWM_CMP_2_FLDMSK                 (0xFFFF0000)


#define PWM3_CFG_REG_0                                  (0x4000091C)

/**
PWM_INIT_VAL, RW, reset value(0x0)
PWM waveform initial value, 1'b1 : PWM waveform start as high; 1'b0 : PWM waveform start as low.
*/
#ifndef PWM_INIT_VAL
#define PWM_INIT_VAL
#endif
#define PWM3_CFG_REG_0_PWM_INIT_VAL                     (0x1F)
#define PWM3_CFG_REG_0_PWM_INIT_VAL_WTH                 (0x01)
#define PWM3_CFG_REG_0_PWM_INIT_VAL_FLDSET              (0x80000000)
#define PWM3_CFG_REG_0_PWM_INIT_VAL_FLDMSK              (0x7FFFFFFF)

/**
PWM_PER, RW, reset value(0x0)
PWM waveform period 
*/
#ifndef PWM_PER
#define PWM_PER
#endif
#define PWM3_CFG_REG_0_PWM_PER                          (0x00)
#define PWM3_CFG_REG_0_PWM_PER_WTH                      (0x10)
#define PWM3_CFG_REG_0_PWM_PER_FLDSET                   (0x0000FFFF)
#define PWM3_CFG_REG_0_PWM_PER_FLDMSK                   (0xFFFF0000)


#define PWM3_CFG_REG_1                                  (0x40000920)

/**
PWM_CMP_1, RW, reset value(0x0)
PWM counter compare point 1, when counter equal to this compare point value, the output is toggled
*/
#ifndef PWM_CMP_1
#define PWM_CMP_1
#endif
#define PWM3_CFG_REG_1_PWM_CMP_1                        (0x10)
#define PWM3_CFG_REG_1_PWM_CMP_1_WTH                    (0x10)
#define PWM3_CFG_REG_1_PWM_CMP_1_FLDSET                 (0xFFFF0000)
#define PWM3_CFG_REG_1_PWM_CMP_1_FLDMSK                 (0x0000FFFF)

/**
PWM_CMP_2, RW, reset value(0x0)
PWM counter compare point 2, when counter equal to this compare point value, the output is toggled
*/
#ifndef PWM_CMP_2
#define PWM_CMP_2
#endif
#define PWM3_CFG_REG_1_PWM_CMP_2                        (0x00)
#define PWM3_CFG_REG_1_PWM_CMP_2_WTH                    (0x10)
#define PWM3_CFG_REG_1_PWM_CMP_2_FLDSET                 (0x0000FFFF)
#define PWM3_CFG_REG_1_PWM_CMP_2_FLDMSK                 (0xFFFF0000)


#define PWM4_CFG_REG_0                                  (0x40000924)

/**
PWM_INIT_VAL, RW, reset value(0x0)
PWM waveform initial value, 1'b1 : PWM waveform start as high; 1'b0 : PWM waveform start as low.
*/
#ifndef PWM_INIT_VAL
#define PWM_INIT_VAL
#endif
#define PWM4_CFG_REG_0_PWM_INIT_VAL                     (0x1F)
#define PWM4_CFG_REG_0_PWM_INIT_VAL_WTH                 (0x01)
#define PWM4_CFG_REG_0_PWM_INIT_VAL_FLDSET              (0x80000000)
#define PWM4_CFG_REG_0_PWM_INIT_VAL_FLDMSK              (0x7FFFFFFF)

/**
PWM_PER, RW, reset value(0x0)
PWM waveform period 
*/
#ifndef PWM_PER
#define PWM_PER
#endif
#define PWM4_CFG_REG_0_PWM_PER                          (0x00)
#define PWM4_CFG_REG_0_PWM_PER_WTH                      (0x10)
#define PWM4_CFG_REG_0_PWM_PER_FLDSET                   (0x0000FFFF)
#define PWM4_CFG_REG_0_PWM_PER_FLDMSK                   (0xFFFF0000)


#define PWM4_CFG_REG_1                                  (0x40000928)

/**
PWM_CMP_1, RW, reset value(0x0)
PWM counter compare point 1, when counter equal to this compare point value, the output is toggled
*/
#ifndef PWM_CMP_1
#define PWM_CMP_1
#endif
#define PWM4_CFG_REG_1_PWM_CMP_1                        (0x10)
#define PWM4_CFG_REG_1_PWM_CMP_1_WTH                    (0x10)
#define PWM4_CFG_REG_1_PWM_CMP_1_FLDSET                 (0xFFFF0000)
#define PWM4_CFG_REG_1_PWM_CMP_1_FLDMSK                 (0x0000FFFF)

/**
PWM_CMP_2, RW, reset value(0x0)
PWM counter compare point 2, when counter equal to this compare point value, the output is toggled
*/
#ifndef PWM_CMP_2
#define PWM_CMP_2
#endif
#define PWM4_CFG_REG_1_PWM_CMP_2                        (0x00)
#define PWM4_CFG_REG_1_PWM_CMP_2_WTH                    (0x10)
#define PWM4_CFG_REG_1_PWM_CMP_2_FLDSET                 (0x0000FFFF)
#define PWM4_CFG_REG_1_PWM_CMP_2_FLDMSK                 (0xFFFF0000)


#define PWM5_CFG_REG_0                                  (0x4000092C)

/**
PWM_INIT_VAL, RW, reset value(0x0)
PWM waveform initial value, 1'b1 : PWM waveform start as high; 1'b0 : PWM waveform start as low.
*/
#ifndef PWM_INIT_VAL
#define PWM_INIT_VAL
#endif
#define PWM5_CFG_REG_0_PWM_INIT_VAL                     (0x1F)
#define PWM5_CFG_REG_0_PWM_INIT_VAL_WTH                 (0x01)
#define PWM5_CFG_REG_0_PWM_INIT_VAL_FLDSET              (0x80000000)
#define PWM5_CFG_REG_0_PWM_INIT_VAL_FLDMSK              (0x7FFFFFFF)

/**
PWM_PER, RW, reset value(0x0)
PWM waveform period 
*/
#ifndef PWM_PER
#define PWM_PER
#endif
#define PWM5_CFG_REG_0_PWM_PER                          (0x00)
#define PWM5_CFG_REG_0_PWM_PER_WTH                      (0x10)
#define PWM5_CFG_REG_0_PWM_PER_FLDSET                   (0x0000FFFF)
#define PWM5_CFG_REG_0_PWM_PER_FLDMSK                   (0xFFFF0000)


#define PWM5_CFG_REG_1                                  (0x40000930)

/**
PWM_CMP_1, RW, reset value(0x0)
PWM counter compare point 1, when counter equal to this compare point value, the output is toggled
*/
#ifndef PWM_CMP_1
#define PWM_CMP_1
#endif
#define PWM5_CFG_REG_1_PWM_CMP_1                        (0x10)
#define PWM5_CFG_REG_1_PWM_CMP_1_WTH                    (0x10)
#define PWM5_CFG_REG_1_PWM_CMP_1_FLDSET                 (0xFFFF0000)
#define PWM5_CFG_REG_1_PWM_CMP_1_FLDMSK                 (0x0000FFFF)

/**
PWM_CMP_2, RW, reset value(0x0)
PWM counter compare point 2, when counter equal to this compare point value, the output is toggled
*/
#ifndef PWM_CMP_2
#define PWM_CMP_2
#endif
#define PWM5_CFG_REG_1_PWM_CMP_2                        (0x00)
#define PWM5_CFG_REG_1_PWM_CMP_2_WTH                    (0x10)
#define PWM5_CFG_REG_1_PWM_CMP_2_FLDSET                 (0x0000FFFF)
#define PWM5_CFG_REG_1_PWM_CMP_2_FLDMSK                 (0xFFFF0000)



#endif /* #ifndef __REG_DEF_PWM_H_ */

