/**
 * \file    drv_adc.h
 * \brief   ADC operations
 *
 * \par     Copyright (c) 2018 UWE Technologies Corp., Ltd. All Rights Reserved.
 * \author  James
 * \date    2018-03-07
 * \version 
 * 
 * \history 
 *  Date        Note
 *  2018-03-07  Original Creation
 * 
 */
 
#ifndef __DRV_ADC_H_
#define __DRV_ADC_H_

#include "types.h"
#include "utils.h"
#include "drv_reg_intf.h"
#include "reg_def_adc.h"

#pragma pack(1)

typedef enum drv_adc_chn_e 
{
    DRV_ADC_CHN_CC1,    // CC1
    DRV_ADC_CHN_CC2,    // CC2
    DRV_ADC_CHN_DP0,    // DP0
    DRV_ADC_CHN_DM0,    // DM0
    DRV_ADC_CHN_DP1,    // DP1
    DRV_ADC_CHN_DM1,    // DM1
    DRV_ADC_CHN_IBUS,   // IBUS: Current Sense
    DRV_ADC_CHN_VBUS,   // VBUS
    DRV_ADC_CHN_8, 
    DRV_ADC_CHN_9,
    DRV_ADC_CHN_10, 
    DRV_ADC_CHN_11,
    DRV_ADC_CHN_12,
    DRV_ADC_CHN_13,
    DRV_ADC_CHN_14,
    DRV_ADC_CHN_15,
    DRV_ADC_CHN_END
} drv_adc_chn_t;

#pragma pack()


/**
 * Set ADC sample time control, in unit of clock cycle
 *
 * \param stc       Clock cycle
 */
void drv_adc_stc_set(u32_t stc);

/**
 * Get ADC sample time control, in unit of clock cycle
 *
 * \return clock cycle
 */
#define drv_adc_stc_get()   DRV_REG_FIELD_GET(ADC_CTRL_REG,ADC_SAMCTRL)

/**
 * ADC channel read
 *
 * \param channel ADC channel, 0 for CC1, 1 for CC2
 * \return 12 bits ADC result
 */
u32_t drv_adc_read(u32_t channel);

/**
 * ADC channel multiple read
 *
 * \param channel   ADC channel, 0 for CC1, 1 for CC2
 * \param count     Reading count
 * \return 12 bits ADC result
 *
 * \see
 */
u32_t drv_adc_read_multi(u32_t channel, u32_t count);

/**
 * ADC channel multiple read and return average value
 *
 * \param channel   ADC channel, 0 for CC1, 1 for CC2
 * \param count     Reading count
 * \return 12 bits ADC average result
 *
 * \see
 */
u32_t drv_adc_read_multi_avg(u32_t channel, u32_t count);

/**
 * ADC channel multiple read, removed the maximal and minimal values then return average value
 *
 * \param channel   ADC channel, 0 for CC1, 1 for CC2
 * \param count     Reading count
 * \return 12 bits ADC average result
 *
 * \see
 */
u32_t drv_adc_read_multi_avg2(u32_t channel, u32_t count);


#define drv_adc_8bits_data_get(input)   (((input)>>(ADC_RSLT_REG_ADC_RSLT_WTH-8))&0xFFU)


typedef enum drv_adc_igain_e 
{
    DRV_ADC_CURRENT_SENSE_GAIN_7,   // 7 times
    DRV_ADC_CURRENT_SENSE_GAIN_15,  // 15 times
    DRV_ADC_CURRENT_SENSE_GAIN_END
} drv_adc_igain_t;


/** \brief Initialize current sense gain
 *
 * \param gain      gain type, see drv_adc_igain_t
 */
void drv_adc_current_sense_init(drv_adc_igain_t gain);

/** \brief Get current sense gain
 *
 * \return current sense gain, see drv_adc_igain_t
 */
drv_adc_igain_t drv_adc_current_sense_gain_get();

/** \brief Get the times of current sense gain
 *
 * \return the times of current sense gain
 */
u32_t drv_adc_current_sense_gain_times_get();

/** \brief Get current sense (ADC6) value
 *
 * \param sample_resister   resistance value of sample resister (milli-ohm)
 * \return  current value (mA)
 */
u32_t drv_adc_ibus_get(u32_t sample_resister);

/** \brief Get current sense direction
 * \return  direction, 0: negative, 1: positive
 */
u8_t drv_adc_ibus_dir_get();


#endif /* #ifndef __DRV_ADC_H_ */


