/**
 * \file    reg_def_adc.h
 * \brief   Register definition file
 * 
 * \par     Copyright (c) 2019 UWE Technologies Corp., Ltd. All Rights Reserved.
 * \author  James
 * \date    2019-04-26
 * \version 
 * 
 * \history 
 *  Date        Note
 *  2019-04-26  Original Creation
 * 
 */

#ifndef __REG_DEF_ADC_H_
#define __REG_DEF_ADC_H_



#define ADC_CTRL_REG                                    (0x40000034)

/**
ADC_REPEAT, RW, reset value(0x1)
ADC read repeat number
*/
#ifndef ADC_REPEAT
#define ADC_REPEAT
#endif
#define ADC_CTRL_REG_ADC_REPEAT                         (0x08)
#define ADC_CTRL_REG_ADC_REPEAT_WTH                     (0x08)
#define ADC_CTRL_REG_ADC_REPEAT_FLDSET                  (0x0000FF00)
#define ADC_CTRL_REG_ADC_REPEAT_FLDMSK                  (0xFFFF00FF)

/**
ADC_RD, RW, reset value(0x0)
SW set 1, and HW clear to this bit to 0 when ADC result is ready
*/
#ifndef ADC_RD
#define ADC_RD
#endif
#define ADC_CTRL_REG_ADC_RD                             (0x07)
#define ADC_CTRL_REG_ADC_RD_WTH                         (0x01)
#define ADC_CTRL_REG_ADC_RD_FLDSET                      (0x00000080)
#define ADC_CTRL_REG_ADC_RD_FLDMSK                      (0xFFFFFF7F)

/**
ADC_SAMCTRL, RW, reset value(0x0)
ADC sample time control (in unit of clock cycle). 
*/
#ifndef ADC_SAMCTRL
#define ADC_SAMCTRL
#endif
#define ADC_CTRL_REG_ADC_SAMCTRL                        (0x04)
#define ADC_CTRL_REG_ADC_SAMCTRL_WTH                    (0x03)
#define ADC_CTRL_REG_ADC_SAMCTRL_FLDSET                 (0x00000070)
#define ADC_CTRL_REG_ADC_SAMCTRL_FLDMSK                 (0xFFFFFF8F)

/**
ADC_CHN, RW, reset value(0x0)
ADC channel select, 3'b000 : CC1; 3'b001: CC2
*/
#ifndef ADC_CHN
#define ADC_CHN
#endif
#define ADC_CTRL_REG_ADC_CHN                            (0x00)
#define ADC_CTRL_REG_ADC_CHN_WTH                        (0x03)
#define ADC_CTRL_REG_ADC_CHN_FLDSET                     (0x00000007)
#define ADC_CTRL_REG_ADC_CHN_FLDMSK                     (0xFFFFFFF8)


#define ADC_RSLT_REG                                    (0x40000038)

/**
ADC_RSLT, RO, reset value(0x0)
ADC result
*/
#ifndef ADC_RSLT
#define ADC_RSLT
#endif
#define ADC_RSLT_REG_ADC_RSLT                           (0x00)
#define ADC_RSLT_REG_ADC_RSLT_WTH                       (0x0C)
#define ADC_RSLT_REG_ADC_RSLT_FLDSET                    (0x00000FFF)
#define ADC_RSLT_REG_ADC_RSLT_FLDMSK                    (0xFFFFF000)



#endif /* #ifndef __REG_DEF_ADC_H_ */

