/**
 * \file    reg_def_uart.h
 * \brief   Register definition file
 * 
 * \par     Copyright (c) 2019 UWE Technologies Corp., Ltd. All Rights Reserved.
 * \author  James
 * \date    2019-04-26
 * \version 
 * 
 * \history 
 *  Date        Note
 *  2019-04-26  Original Creation
 * 
 */

#ifndef __REG_DEF_UART_H_
#define __REG_DEF_UART_H_



#define UART_PBR_REG                                    (0x40000500)

/**
RXD, RO, reset value(0x0)
Receive Bufffer Data register, content is only valid when LSR[DR] = 1'b1 and access select by LCR[7] = 1'b0.
*/
#ifndef RXD
#define RXD
#endif
#define UART_PBR_REG_RXD                                (0x00)
#define UART_PBR_REG_RXD_WTH                            (0x08)
#define UART_PBR_REG_RXD_FLDSET                         (0x000000FF)
#define UART_PBR_REG_RXD_FLDMSK                         (0xFFFFFF00)


#define UART_THR_REG                                    (0x40000504)

/**
THR, WO, reset value(0x0)
Transmit Data Register, content could be written only when LSR[THRE]=1'b1 and access select by LCR[7] = 1'b0.
*/
#ifndef THR
#define THR
#endif
#define UART_THR_REG_THR                                (0x00)
#define UART_THR_REG_THR_WTH                            (0x08)
#define UART_THR_REG_THR_FLDSET                         (0x000000FF)
#define UART_THR_REG_THR_FLDMSK                         (0xFFFFFF00)


#define UART_DLL_REG                                    (0x40000508)

/**
DLL, RW, reset value(0x0)
Frequency divider LSB register, access select by LCR[7] = 1'b1.
*/
#ifndef DLL
#define DLL
#endif
#define UART_DLL_REG_DLL                                (0x00)
#define UART_DLL_REG_DLL_WTH                            (0x08)
#define UART_DLL_REG_DLL_FLDSET                         (0x000000FF)
#define UART_DLL_REG_DLL_FLDMSK                         (0xFFFFFF00)


#define UART_DLH_REG                                    (0x4000050C)

/**
DLH, RW, reset value(0x0)
Frequency divider MSB register, access select by LCR[7] = 1'b1.
*/
#ifndef DLH
#define DLH
#endif
#define UART_DLH_REG_DLH                                (0x00)
#define UART_DLH_REG_DLH_WTH                            (0x08)
#define UART_DLH_REG_DLH_FLDSET                         (0x000000FF)
#define UART_DLH_REG_DLH_FLDMSK                         (0xFFFFFF00)


#define UART_IER_REG                                    (0x40000510)

/**
ELSI, RW, reset value(0x0)
Enable receive status interrupt, access select by LCR[7] = 1'b0.
*/
#ifndef ELSI
#define ELSI
#endif
#define UART_IER_REG_ELSI                               (0x02)
#define UART_IER_REG_ELSI_WTH                           (0x01)
#define UART_IER_REG_ELSI_FLDSET                        (0x00000004)
#define UART_IER_REG_ELSI_FLDMSK                        (0xFFFFFFFB)

/**
ETBEI, RW, reset value(0x0)
Enable transmit data register empty interrupt
*/
#ifndef ETBEI
#define ETBEI
#endif
#define UART_IER_REG_ETBEI                              (0x01)
#define UART_IER_REG_ETBEI_WTH                          (0x01)
#define UART_IER_REG_ETBEI_FLDSET                       (0x00000002)
#define UART_IER_REG_ETBEI_FLDMSK                       (0xFFFFFFFD)

/**
ERBFI, RW, reset value(0x0)
Enable receive data active interrupt
*/
#ifndef ERBFI
#define ERBFI
#endif
#define UART_IER_REG_ERBFI                              (0x00)
#define UART_IER_REG_ERBFI_WTH                          (0x01)
#define UART_IER_REG_ERBFI_FLDSET                       (0x00000001)
#define UART_IER_REG_ERBFI_FLDMSK                       (0xFFFFFFFE)


#define UART_IIR_REG                                    (0x40000514)

/**
IID, RO, reset value(0x1)
4'b0001 : No interrupt
4'b0010 : THR empty interrupt
4'b0100 : RXD active interrupt, receive data is active event will generate this interrupt.
4'b0110 : Receive Status interrupt; overrun error, frame error and parity check error events will generate this interrupt.
4'b0111 : UART is busy interrupt
*/
#ifndef IID
#define IID
#endif
#define UART_IIR_REG_IID                                (0x00)
#define UART_IIR_REG_IID_WTH                            (0x04)
#define UART_IIR_REG_IID_FLDSET                         (0x0000000F)
#define UART_IIR_REG_IID_FLDMSK                         (0xFFFFFFF0)


#define UART_LCR_REG                                    (0x40000518)

/**
DLAB, RW, reset value(0x0)
Register access selection.
*/
#ifndef DLAB
#define DLAB
#endif
#define UART_LCR_REG_DLAB                               (0x07)
#define UART_LCR_REG_DLAB_WTH                           (0x01)
#define UART_LCR_REG_DLAB_FLDSET                        (0x00000080)
#define UART_LCR_REG_DLAB_FLDMSK                        (0xFFFFFF7F)

/**
FCTL_EN, RW, reset value(0x0)
UART with flow control signals "RTS/CTS" enable
*/
#ifndef FCTL_EN
#define FCTL_EN
#endif
#define UART_LCR_REG_FCTL_EN                            (0x06)
#define UART_LCR_REG_FCTL_EN_WTH                        (0x01)
#define UART_LCR_REG_FCTL_EN_FLDSET                     (0x00000040)
#define UART_LCR_REG_FCTL_EN_FLDMSK                     (0xFFFFFFBF)

/**
EPS, RW, reset value(0x0)
Parity check select, 1'b1 : even parity check; 1'b0 : odd parity check.
*/
#ifndef EPS
#define EPS
#endif
#define UART_LCR_REG_EPS                                (0x04)
#define UART_LCR_REG_EPS_WTH                            (0x01)
#define UART_LCR_REG_EPS_FLDSET                         (0x00000010)
#define UART_LCR_REG_EPS_FLDMSK                         (0xFFFFFFEF)

/**
PEN, RW, reset value(0x0)
Parity check enable
*/
#ifndef PEN
#define PEN
#endif
#define UART_LCR_REG_PEN                                (0x03)
#define UART_LCR_REG_PEN_WTH                            (0x01)
#define UART_LCR_REG_PEN_FLDSET                         (0x00000008)
#define UART_LCR_REG_PEN_FLDMSK                         (0xFFFFFFF7)

/**
STOP, RW, reset value(0x0)
Stop bit number, 1'b0 : one stop bit, 1'b1 : two stop bits.
*/
#ifndef STOP
#define STOP
#endif
#define UART_LCR_REG_STOP                               (0x02)
#define UART_LCR_REG_STOP_WTH                           (0x01)
#define UART_LCR_REG_STOP_FLDSET                        (0x00000004)
#define UART_LCR_REG_STOP_FLDMSK                        (0xFFFFFFFB)

/**
DLS, RW, reset value(0x0)
data length select: 
2'b00 : 5 bits
2'b01 : 6 bits
2'b10 : 7 bits
2'b11 : 8 bits
*/
#ifndef DLS
#define DLS
#endif
#define UART_LCR_REG_DLS                                (0x00)
#define UART_LCR_REG_DLS_WTH                            (0x02)
#define UART_LCR_REG_DLS_FLDSET                         (0x00000003)
#define UART_LCR_REG_DLS_FLDMSK                         (0xFFFFFFFC)


#define UART_LSR_REG                                    (0x4000051C)

/**
TEMT, RO, reset value(0x1)
1'b1 : Both THR and transmit shift register is empty
*/
#ifndef TEMT
#define TEMT
#endif
#define UART_LSR_REG_TEMT                               (0x06)
#define UART_LSR_REG_TEMT_WTH                           (0x01)
#define UART_LSR_REG_TEMT_FLDSET                        (0x00000040)
#define UART_LSR_REG_TEMT_FLDMSK                        (0xFFFFFFBF)

/**
THRE, RO, reset value(0x1)
1'b1 : THR is empty
*/
#ifndef THRE
#define THRE
#endif
#define UART_LSR_REG_THRE                               (0x05)
#define UART_LSR_REG_THRE_WTH                           (0x01)
#define UART_LSR_REG_THRE_FLDSET                        (0x00000020)
#define UART_LSR_REG_THRE_FLDMSK                        (0xFFFFFFDF)

/**
FE, RO, reset value(0x0)
1'b1 : frame error
*/
#ifndef FE
#define FE
#endif
#define UART_LSR_REG_FE                                 (0x03)
#define UART_LSR_REG_FE_WTH                             (0x01)
#define UART_LSR_REG_FE_FLDSET                          (0x00000008)
#define UART_LSR_REG_FE_FLDMSK                          (0xFFFFFFF7)

/**
PE, RO, reset value(0x0)
1'b1 : parity check error
*/
#ifndef PE
#define PE
#endif
#define UART_LSR_REG_PE                                 (0x02)
#define UART_LSR_REG_PE_WTH                             (0x01)
#define UART_LSR_REG_PE_FLDSET                          (0x00000004)
#define UART_LSR_REG_PE_FLDMSK                          (0xFFFFFFFB)

/**
OE, RO, reset value(0x0)
1'b1 : active data is override error
*/
#ifndef OE
#define OE
#endif
#define UART_LSR_REG_OE                                 (0x01)
#define UART_LSR_REG_OE_WTH                             (0x01)
#define UART_LSR_REG_OE_FLDSET                          (0x00000002)
#define UART_LSR_REG_OE_FLDMSK                          (0xFFFFFFFD)

/**
DR, RO, reset value(0x0)
1'b1 : receive data is active
*/
#ifndef DR
#define DR
#endif
#define UART_LSR_REG_DR                                 (0x00)
#define UART_LSR_REG_DR_WTH                             (0x01)
#define UART_LSR_REG_DR_FLDSET                          (0x00000001)
#define UART_LSR_REG_DR_FLDMSK                          (0xFFFFFFFE)


#define UART_USR_REG                                    (0x40000520)

/**
BUSY, RO, reset value(0x0)
1'b1 : UART is busy
*/
#ifndef BUSY
#define BUSY
#endif
#define UART_USR_REG_BUSY                               (0x00)
#define UART_USR_REG_BUSY_WTH                           (0x01)
#define UART_USR_REG_BUSY_FLDSET                        (0x00000001)
#define UART_USR_REG_BUSY_FLDMSK                        (0xFFFFFFFE)


#define SEC_UART_PBR_REG                                (0x40000600)

/**
RXD, RO, reset value(0x0)
Receive Bufffer Data register, content is only valid when LSR[DR] = 1'b1 and access select by LCR[7] = 1'b0.
*/
#ifndef RXD
#define RXD
#endif
#define SEC_UART_PBR_REG_RXD                            (0x00)
#define SEC_UART_PBR_REG_RXD_WTH                        (0x08)
#define SEC_UART_PBR_REG_RXD_FLDSET                     (0x000000FF)
#define SEC_UART_PBR_REG_RXD_FLDMSK                     (0xFFFFFF00)


#define SEC_UART_THR_REG                                (0x40000604)

/**
THR, WO, reset value(0x0)
Transmit Data Register, content could be written only when LSR[THRE]=1'b1 and access select by LCR[7] = 1'b0.
*/
#ifndef THR
#define THR
#endif
#define SEC_UART_THR_REG_THR                            (0x00)
#define SEC_UART_THR_REG_THR_WTH                        (0x08)
#define SEC_UART_THR_REG_THR_FLDSET                     (0x000000FF)
#define SEC_UART_THR_REG_THR_FLDMSK                     (0xFFFFFF00)


#define SEC_UART_DLL_REG                                (0x40000608)

/**
DLL, RW, reset value(0x0)
Frequency divider LSB register, access select by LCR[7] = 1'b1.
*/
#ifndef DLL
#define DLL
#endif
#define SEC_UART_DLL_REG_DLL                            (0x00)
#define SEC_UART_DLL_REG_DLL_WTH                        (0x08)
#define SEC_UART_DLL_REG_DLL_FLDSET                     (0x000000FF)
#define SEC_UART_DLL_REG_DLL_FLDMSK                     (0xFFFFFF00)


#define SEC_UART_DLH_REG                                (0x4000060C)

/**
DLH, RW, reset value(0x0)
Frequency divider MSB register, access select by LCR[7] = 1'b1.
*/
#ifndef DLH
#define DLH
#endif
#define SEC_UART_DLH_REG_DLH                            (0x00)
#define SEC_UART_DLH_REG_DLH_WTH                        (0x08)
#define SEC_UART_DLH_REG_DLH_FLDSET                     (0x000000FF)
#define SEC_UART_DLH_REG_DLH_FLDMSK                     (0xFFFFFF00)


#define SEC_UART_IER_REG                                (0x40000610)

/**
ELSI, RW, reset value(0x0)
Enable receive status interrupt, access select by LCR[7] = 1'b0.
*/
#ifndef ELSI
#define ELSI
#endif
#define SEC_UART_IER_REG_ELSI                           (0x02)
#define SEC_UART_IER_REG_ELSI_WTH                       (0x01)
#define SEC_UART_IER_REG_ELSI_FLDSET                    (0x00000004)
#define SEC_UART_IER_REG_ELSI_FLDMSK                    (0xFFFFFFFB)

/**
ETBEI, RW, reset value(0x0)
Enable transmit data register empty interrupt
*/
#ifndef ETBEI
#define ETBEI
#endif
#define SEC_UART_IER_REG_ETBEI                          (0x01)
#define SEC_UART_IER_REG_ETBEI_WTH                      (0x01)
#define SEC_UART_IER_REG_ETBEI_FLDSET                   (0x00000002)
#define SEC_UART_IER_REG_ETBEI_FLDMSK                   (0xFFFFFFFD)

/**
ERBFI, RW, reset value(0x0)
Enable receive data active interrupt
*/
#ifndef ERBFI
#define ERBFI
#endif
#define SEC_UART_IER_REG_ERBFI                          (0x00)
#define SEC_UART_IER_REG_ERBFI_WTH                      (0x01)
#define SEC_UART_IER_REG_ERBFI_FLDSET                   (0x00000001)
#define SEC_UART_IER_REG_ERBFI_FLDMSK                   (0xFFFFFFFE)


#define SEC_UART_IIR_REG                                (0x40000614)

/**
IID, RO, reset value(0x1)
4'b0001 : No interrupt
4'b0010 : THR empty interrupt
4'b0100 : RXD active interrupt
4'b0110 : Receive Status interrupt
4'b0111 : UART is busy interrupt
*/
#ifndef IID
#define IID
#endif
#define SEC_UART_IIR_REG_IID                            (0x00)
#define SEC_UART_IIR_REG_IID_WTH                        (0x04)
#define SEC_UART_IIR_REG_IID_FLDSET                     (0x0000000F)
#define SEC_UART_IIR_REG_IID_FLDMSK                     (0xFFFFFFF0)


#define SEC_UART_LCR_REG                                (0x40000618)

/**
DLAB, RW, reset value(0x0)
Register access selection.
*/
#ifndef DLAB
#define DLAB
#endif
#define SEC_UART_LCR_REG_DLAB                           (0x07)
#define SEC_UART_LCR_REG_DLAB_WTH                       (0x01)
#define SEC_UART_LCR_REG_DLAB_FLDSET                    (0x00000080)
#define SEC_UART_LCR_REG_DLAB_FLDMSK                    (0xFFFFFF7F)

/**
FCTL_EN, RW, reset value(0x0)
UART with flow control signals "RTS/CTS" enable
*/
#ifndef FCTL_EN
#define FCTL_EN
#endif
#define SEC_UART_LCR_REG_FCTL_EN                        (0x06)
#define SEC_UART_LCR_REG_FCTL_EN_WTH                    (0x01)
#define SEC_UART_LCR_REG_FCTL_EN_FLDSET                 (0x00000040)
#define SEC_UART_LCR_REG_FCTL_EN_FLDMSK                 (0xFFFFFFBF)

/**
EPS, RW, reset value(0x0)
Parity check select, 1'b1 : even parity check; 1'b0 : odd parity check.
*/
#ifndef EPS
#define EPS
#endif
#define SEC_UART_LCR_REG_EPS                            (0x04)
#define SEC_UART_LCR_REG_EPS_WTH                        (0x01)
#define SEC_UART_LCR_REG_EPS_FLDSET                     (0x00000010)
#define SEC_UART_LCR_REG_EPS_FLDMSK                     (0xFFFFFFEF)

/**
PEN, RW, reset value(0x0)
Parity check enable
*/
#ifndef PEN
#define PEN
#endif
#define SEC_UART_LCR_REG_PEN                            (0x03)
#define SEC_UART_LCR_REG_PEN_WTH                        (0x01)
#define SEC_UART_LCR_REG_PEN_FLDSET                     (0x00000008)
#define SEC_UART_LCR_REG_PEN_FLDMSK                     (0xFFFFFFF7)

/**
STOP, RW, reset value(0x0)
Stop bit number, 1'b0 : one stop bit, 1'b1 : two stop bits.
*/
#ifndef STOP
#define STOP
#endif
#define SEC_UART_LCR_REG_STOP                           (0x02)
#define SEC_UART_LCR_REG_STOP_WTH                       (0x01)
#define SEC_UART_LCR_REG_STOP_FLDSET                    (0x00000004)
#define SEC_UART_LCR_REG_STOP_FLDMSK                    (0xFFFFFFFB)

/**
DLS, RW, reset value(0x0)
data length select: 
2'b00 : 5 bits
2'b01 : 6 bits
2'b10 : 7 bits
2'b11 : 8 bits
*/
#ifndef DLS
#define DLS
#endif
#define SEC_UART_LCR_REG_DLS                            (0x00)
#define SEC_UART_LCR_REG_DLS_WTH                        (0x02)
#define SEC_UART_LCR_REG_DLS_FLDSET                     (0x00000003)
#define SEC_UART_LCR_REG_DLS_FLDMSK                     (0xFFFFFFFC)


#define SEC_UART_LSR_REG                                (0x4000061C)

/**
TEMT, RO, reset value(0x1)
1'b1 : Both THR and transmit shift register is empty
*/
#ifndef TEMT
#define TEMT
#endif
#define SEC_UART_LSR_REG_TEMT                           (0x06)
#define SEC_UART_LSR_REG_TEMT_WTH                       (0x01)
#define SEC_UART_LSR_REG_TEMT_FLDSET                    (0x00000040)
#define SEC_UART_LSR_REG_TEMT_FLDMSK                    (0xFFFFFFBF)

/**
THRE, RO, reset value(0x1)
1'b1 : THR is empty
*/
#ifndef THRE
#define THRE
#endif
#define SEC_UART_LSR_REG_THRE                           (0x05)
#define SEC_UART_LSR_REG_THRE_WTH                       (0x01)
#define SEC_UART_LSR_REG_THRE_FLDSET                    (0x00000020)
#define SEC_UART_LSR_REG_THRE_FLDMSK                    (0xFFFFFFDF)

/**
FE, RO, reset value(0x0)
1'b1 : frame error
*/
#ifndef FE
#define FE
#endif
#define SEC_UART_LSR_REG_FE                             (0x03)
#define SEC_UART_LSR_REG_FE_WTH                         (0x01)
#define SEC_UART_LSR_REG_FE_FLDSET                      (0x00000008)
#define SEC_UART_LSR_REG_FE_FLDMSK                      (0xFFFFFFF7)

/**
PE, RO, reset value(0x0)
1'b1 : parity check error
*/
#ifndef PE
#define PE
#endif
#define SEC_UART_LSR_REG_PE                             (0x02)
#define SEC_UART_LSR_REG_PE_WTH                         (0x01)
#define SEC_UART_LSR_REG_PE_FLDSET                      (0x00000004)
#define SEC_UART_LSR_REG_PE_FLDMSK                      (0xFFFFFFFB)

/**
OE, RO, reset value(0x0)
1'b1 : active data is override error
*/
#ifndef OE
#define OE
#endif
#define SEC_UART_LSR_REG_OE                             (0x01)
#define SEC_UART_LSR_REG_OE_WTH                         (0x01)
#define SEC_UART_LSR_REG_OE_FLDSET                      (0x00000002)
#define SEC_UART_LSR_REG_OE_FLDMSK                      (0xFFFFFFFD)

/**
DR, RO, reset value(0x0)
1'b1 : receive data is active
*/
#ifndef DR
#define DR
#endif
#define SEC_UART_LSR_REG_DR                             (0x00)
#define SEC_UART_LSR_REG_DR_WTH                         (0x01)
#define SEC_UART_LSR_REG_DR_FLDSET                      (0x00000001)
#define SEC_UART_LSR_REG_DR_FLDMSK                      (0xFFFFFFFE)


#define SEC_UART_USR_REG                                (0x40000620)

/**
BUSY, RO, reset value(0x0)
1'b1 : UART is busy
*/
#ifndef BUSY
#define BUSY
#endif
#define SEC_UART_USR_REG_BUSY                           (0x00)
#define SEC_UART_USR_REG_BUSY_WTH                       (0x01)
#define SEC_UART_USR_REG_BUSY_FLDSET                    (0x00000001)
#define SEC_UART_USR_REG_BUSY_FLDMSK                    (0xFFFFFFFE)



#endif /* #ifndef __REG_DEF_UART_H_ */

