/**
 * \file    sys_reg.h
 * \brief   System control register definitions header file
 *
 * \par     Copyright (c) 2020 UWE Technologies Corp., Ltd. All Rights Reserved.
 * \author  James
 * \date    2020-03-27
 * \version
 *
 * \history
 *  Date        Note
 *  2020-03-27  Original Creation
 *
 */

#ifndef __SYS_REG_H_
#define __SYS_REG_H_

#ifdef __cplusplus
extern "C" {
#endif

#include "types.h"

/** System control register definitions */


#define SYS_FW_UPDATE_CMD_REG           (0x50)
#define SYS_FW_UPDATE_STA_REG           (0x51)
#define SYS_FW_INFO_REG                 (0x52)
#define SYS_FW_DATA_REG                 (0x60)


#define SYS_SLA_DEV_ID                  (0x28)
#define SYS_SLA_VERSION                 (0x01)

#pragma pack(1)
typedef enum SYS_FW_UPDATE_STA_s
{
    FW_UPDATE_STA_IDLE,
    FW_UPDATE_STA_START,
    FW_UPDATE_STA_START_INFO,
    FW_UPDATE_STA_STOP   
}SYS_FW_UPDATE_STA_t;

/** mcu ctr fw update cmd*/
typedef struct SYS_REG_MAST_FW_UPDATE_CTRL_s
{
    unsigned char cmd:3,                  /* Master ctrl Fw update*/
                  resv:5;                 /* reserv */
} SYS_REG_MAST_FW_UPDATE_CTRL_t;

/** Fw update sta */
typedef struct SYS_REG_FW_UPDATE_STA_s
{
    unsigned char sta0:3,                   /* Fw update sta*/
                  mode:1,                   /*1:app, 0:bootload*/
                  ready:1,                  /*en transmit data */
                  err:1,                    /*fw update err*/
                  process:1,               /*on download fw process*/
                  finish:1;                 /*fw download finish*/
} SYS_REG_FW_UPDATE_STA_t;

/** Fw info */
typedef struct SYS_REG_FW_INFO_s
{
   unsigned char lenth[3];
   unsigned char crc[2];
} SYS_REG_FW_INFO_t;


/** System Control 1 Register */
typedef struct SYS_CONTROL_1_REG_s
{
    unsigned char cfg_save:1,               /* Save configuration */
                  cfg_erase:1,              /* Erase configuration */
                  reserved:6;               /* Reserved */
} SYS_CONTROL_1_REG_t;


typedef struct DPM_FW_UDATE_RESV_MEM_s 
{
    u32_t fw_update_flg:1;
    u32_t fw_update_code:8;
    u32_t fw_app_init:1;
    u32_t resv:22;
}DPM_FW_UDATE_RESV_MEM_t;

typedef struct SYS_FW_UPDATE_s
{
   u32_t mcu_ctrl_fw_cmd:3;
   u32_t rx_fw_info_flg:1;
   u32_t rx_fw_data_flg:1;
   u32_t i2c_slave_tx_start_flg:1;
   u32_t resv0:26;

   u32_t crc:16;
   u8_t  i2c_sla_tx_reg:8;
   u32_t s_rx_fw_data_lenth:8;
   
   u32_t lenth;
   
   SYS_REG_FW_UPDATE_STA_t sla_sta;
   
} SYS_FW_UPDATE_t;

extern volatile DPM_FW_UDATE_RESV_MEM_t *fw_udate_resv_mem_ptr ;
extern volatile SYS_FW_UPDATE_t g_sys_fw_update;

void fw_update_init(void);

#pragma pack()
#if 0
bool_t sys_version_reg_get(unsigned char *p_val);
bool_t sys_control_0_reg_get(unsigned char *p_val);
bool_t sys_control_0_reg_set(unsigned char *p_val);
bool_t sys_src_pwr_profile_reg_get(unsigned char *p_val);
bool_t sys_src_pwr_profile_reg_set(unsigned char *p_val);
bool_t sys_snk_pwr_profile_reg_get(unsigned char *p_val);
bool_t sys_snk_pwr_profile_reg_set(unsigned char *p_val);
bool_t sys_battery_cap_reg_get(unsigned char *p_val);
bool_t sys_battery_cap_reg_set(unsigned char *p_val);
bool_t sys_event_0_reg_get(unsigned char *p_val);
bool_t sys_event_0_reg_set(unsigned char *p_val);
bool_t sys_event_1_reg_get(unsigned char *p_val);
bool_t sys_event_1_reg_set(unsigned char *p_val);
bool_t sys_control_1_reg_get(unsigned char *p_val);
bool_t sys_control_1_reg_set(unsigned char *p_val);
bool_t sys_operating_pwr_reg_get(unsigned char *p_val);
bool_t sys_ntc_val_0_reg_get(unsigned char *p_val);
bool_t sys_ntc_val_1_reg_get(unsigned char *p_val);
bool_t sys_ntc_val_0_reg_set(unsigned char *p_val);
bool_t sys_ntc_val_1_reg_set(unsigned char *p_val);

bool_t sys_type_c_ctrl_reg_get(unsigned char *p_val);
bool_t sys_type_c_ctrl_reg_set(unsigned char *p_val);
bool_t sys_pd_ctrl_reg_get(unsigned char *p_val);
bool_t sys_pd_ctrl_reg_set(unsigned char *p_val);
bool_t sys_qc_ctrl_reg_get(unsigned char *p_val);
bool_t sys_qc_ctrl_reg_set(unsigned char *p_val);
bool_t sys_adv_ctrl_0_reg_get(unsigned char *p_val);
bool_t sys_adv_ctrl_0_reg_set(unsigned char *p_val);
bool_t sys_adv_ctrl_1_reg_get(unsigned char *p_val);
bool_t sys_adv_ctrl_1_reg_set(unsigned char *p_val);
bool_t sys_pdo_ctrl_reg_get(unsigned char *p_val);
bool_t sys_pdo_ctrl_reg_set(unsigned char *p_val);
bool_t sys_pdo_byte_0_reg_get(unsigned char *p_val);
bool_t sys_pdo_byte_0_reg_set(unsigned char *p_val);
bool_t sys_pdo_byte_1_reg_get(unsigned char *p_val);
bool_t sys_pdo_byte_1_reg_set(unsigned char *p_val);
bool_t sys_pdo_byte_2_reg_get(unsigned char *p_val);
bool_t sys_pdo_byte_2_reg_set(unsigned char *p_val);
bool_t sys_pdo_byte_3_reg_get(unsigned char *p_val);
bool_t sys_pdo_byte_3_reg_set(unsigned char *p_val);

bool_t sys_type_c_status_0_reg_get(unsigned char *p_val);
bool_t sys_pd_status_reg_get(unsigned char *p_val);
bool_t sys_qc_status_reg_get(unsigned char *p_val);
bool_t sys_type_c_status_1_reg_get(unsigned char *p_val);
bool_t sys_pe_status_reg_get(unsigned char *p_val);
bool_t sys_vbus_val_0_reg_get(unsigned char *p_val);
bool_t sys_vbus_val_1_reg_get(unsigned char *p_val);
bool_t sys_ibus_val_0_reg_get(unsigned char *p_val);
bool_t sys_ibus_val_1_reg_get(unsigned char *p_val);

bool_t sys_chip_reg_ctrl_reg_get(unsigned char *p_val);
bool_t sys_chip_reg_addr_0_reg_get(unsigned char *p_val);
bool_t sys_chip_reg_addr_1_reg_get(unsigned char *p_val);
bool_t sys_chip_reg_addr_2_reg_get(unsigned char *p_val);
bool_t sys_chip_reg_addr_3_reg_get(unsigned char *p_val);
bool_t sys_chip_reg_val_0_reg_get(unsigned char *p_val);
bool_t sys_chip_reg_val_1_reg_get(unsigned char *p_val);
bool_t sys_chip_reg_val_2_reg_get(unsigned char *p_val);
bool_t sys_chip_reg_val_3_reg_get(unsigned char *p_val);

bool_t sys_chip_reg_ctrl_reg_set(unsigned char *p_val);
bool_t sys_chip_reg_addr_0_reg_set(unsigned char *p_val);
bool_t sys_chip_reg_addr_1_reg_set(unsigned char *p_val);
bool_t sys_chip_reg_addr_2_reg_set(unsigned char *p_val);
bool_t sys_chip_reg_addr_3_reg_set(unsigned char *p_val);
bool_t sys_chip_reg_val_0_reg_set(unsigned char *p_val);
bool_t sys_chip_reg_val_1_reg_set(unsigned char *p_val);
bool_t sys_chip_reg_val_2_reg_set(unsigned char *p_val);
bool_t sys_chip_reg_val_3_reg_set(unsigned char *p_val);

bool_t sys_chip_adc_ctrl_reg_get(unsigned char *p_val);
bool_t sys_chip_adc_ctrl_reg_set(unsigned char *p_val);
bool_t sys_chip_adc_val_0_reg_get(unsigned char *p_val);
bool_t sys_chip_adc_val_1_reg_get(unsigned char *p_val);

bool_t sys_reg_read(unsigned char reg, unsigned char *p_val);
bool_t sys_reg_write(unsigned char reg, unsigned char *p_val);
bool_t sys_fw_update_cmd_reg_set(unsigned char *p_val);

#endif
#ifdef __cplusplus
}
#endif

#endif /* #ifndef __SYS_REG_H_ */

