/**
 * \file    platform_config.h
 * \brief   Architecture specific defs and inlines
 * 
 * \par     Copyright (c) 2018 UWE Technologies Corp., Ltd. All Rights Reserved.
 * \author  James
 * \date    2018-03-12
 * \version 
 * 
 * \history 
 *  Date        Note
 *  2018-03-12  Original Creation
 * 
 */
 
#ifndef __PLATFORM_CONFIG_H_
#define __PLATFORM_CONFIG_H_

#include <stdint.h>
#include <stdbool.h>


/** printf library enabled, disable it will save code size */
#define LIBC_PRINTF_ENABLED                 (1)


/** BSP GPIO driver debug enable */
#define DRV_DBG_GPIO_ENABLED                (0)


/** FPGA mode definition */
#define FPGA_MODE                           (0)

/** CLI enabled */
#define CLI_ENABLED                         (1)

/** FLASH enabled */
#define FLASH_ENABLED                       (1)

/** Bootloader enabled */
#define BOOT_LOADER_ENABLED                 (0)

/** Bootloader start address */
#define BOOT_ADDR_OFFSET                    (0x0UL)

/** App start address */
#define APP_ADDR_OFFSET                     (0x4000UL)

/** APP_IMG_SIZE defined the max length(byte) of a image code */
#define APP_IMG_SIZE                        (0x3C000UL)

/** Configuration is saved in Security Register 1 
 *  Security Register 1: A23-16=00h, A15-8=10h, A7-0=byte address
 */
#define CFG_ADDR                            (0x1000UL)

/** CFG_SIZE defined the max length(byte) of the configuration */
#define CFG_SIZE                            (0x100U)

/** Trim codes is saved in Security Register 2 
 *  Security Register 2: A23-16=00h, A15-8=20h, A7-0=byte address
 */
#define TRIM_CODES_ADDR                     (0x2000U)
#define TRIM_CODES_ADDR_MASK                (0xDF00U)

/** UART interrupt enabled */
#define UART_INTR_ENABLED                   (1)

/** UART1 test enabled */
#define UART1_TEST_ENABLED                  (1)
#define UART1_DMA_ENABLED                   (0)


/** Enable SPI module */
#define SPI_MODULE_ENABLED                  (1)
/** Enable SPI SLAVE MODE */
#define SPI_MODULE_SLAVE_ENABLED            (0)
/** Enable DMA copy in SPI SLAVE MODE */
#define SPI_MODULE_SLAVE_DMA_ENABLED        (0)


/** Enable I2C module */
#define I2C_MODULE_ENABLED                  (1)
/** Enable I2C slave mode */
#define I2C_MODULE_SLA_ENABLED              (1)
/** Enable I2C register access mode */
#define I2C_MODULE_REG_ENABLED              (1)
/** Enable I2C 16 bits register access mode */
#define I2C_MODULE_REG_16_ENABLED           (1)
/** Enable I2C interrupt service request debugging */
#define I2C_ISR_DBG_ENABLED                 (1)
/** Enable I2C slave callback function mode */
#define I2C_SLA_CB_ENABLED                  (0)


/** Enable hardware DMA memory copy */
#define DMA_MEMCPY_ENABLED                  (1)

/** Low power enabled */
#define LOW_POWER_ENABLED                   (0)

/** Reserved memmory allocation */
#define RESV_MEM_ADDR_START                 (0x60000000)
#define RESV_MEM_ADDR_END                   (0x60000294)
#define RESV_MEM_PD_PRL_RX_DMA_START        (RESV_MEM_ADDR_START)
#define RESV_MEM_PD_DPM_START               (RESV_MEM_ADDR_START+640)

/** Enable FreeRTOS */
#define SYS_FREERTOS_ENABLED                (0)
#if (SYS_FREERTOS_ENABLED)
/** If enabled FreeRTOS, disable SAL message queue */
#define SAL_MSQ_ENABLED                     (0)
/** 
 * If Enabled FreeRTOS Then 
 *    RISC-V embedded machine timer is used for task scheduling 
 *    So need to disable driver level mtimer
 * Endif
 */
#define SYS_DRIVER_M_TIMER_ENABLED          (0)
#else
/** If disabled FreeRTOS, Enable SAL message queue */
#define SAL_MSQ_ENABLED                     (1)
/** 
 * If Disabled FreeRTOS Then 
 *    RISC-V embedded machine timer is IDLE 
 *    So User can enable driver level mtimer
 * Endif
 */
#define SYS_DRIVER_M_TIMER_ENABLED          (1)
#endif

/** RISC-V embedded machine timer period, 1ms, unit in us */
#define SYS_DRIVER_TIMER_PERIOD             (1000)


/** Enable USB Power Delivery Module */
#define USB_PD_MODULE_ENABLED               (0)


/** ADC reference voltage, divisor  */
#if FPGA_MODE
#define ADC_REF_VOLTAGE                     (5000U)
#else
#define ADC_REF_VOLTAGE                     (3300U)
#endif
#define ADC_REF_DIVISOR                     (4096U)

#define ADC_CURRENT_SENSE_DIVISOR           (1U)

/** VBUS ADC reference voltage constant 
 *  VBUS Voltage = ADC_RESULT * ADC_REF_VOLTAGE * VBUS_ADC_CONSTANT / ADC_REF_DIVISOR
 */
#define VBUS_ADC_CONSTANT                   (8U)


/** vSafe0V range: 0 ~ 0.8V, we use 799mV as the max vSafe0V */
//#define VBUS_VSAFE0V_MAX_ADC                (((799.0*ADC_REF_DIVISOR)/(ADC_REF_VOLTAGE*VBUS_ADC_CONSTANT))-1)
#define VBUS_VSAFE0V_MAX_ADC                (0x7C)

/** vSafe0V range: 0 ~ 0.8V, we use 799mV as the max vSafe0V */
#define VBUS_VSAFE0V_MAX_VOLT               (799)


#endif /* #ifndef __PLATFORM_CONFIG_H_ */
