/**
* \file    dpm_port.h
* \brief   Device manager interfaces
*
* \par     Copyright (c) 2018 UWE Technologies Corp., Ltd. All Rights Reserved.
* \author  James
* \date    2018-03-05
* \version
*
* \history
*  Date        Note
*  2018-03-05  Original Creation
*
*/

#ifndef __DPM_PORT_H_
#define __DPM_PORT_H_


#include "types.h"
#include "usbpd_defs.h"
#include "reg_def_pd.h"
#include "drivers.h"
#include "prl_msg_parser.h"
#include "prl_msg_defs.h"
#include "usbpd_hook.h"

#pragma pack(1)

/** VBUS voltage threshold, min and max  */
#define VBUS_VOLT_MIN_THR           (0.90)
#define VBUS_VOLT_MAX_THR           (1.10)

#define VBUS_VOLT_DROP_MIN_THR      (0.85)
#define VBUS_VOLT_OVP_MAX_THR       (1.12)

#define DPM_BIST_TEST_DATA_SIZE     (24)

typedef enum DPM_SOP_CAB_TYPE_e
{
    DPM_SOP_CAB_TYPE_RX_SOP_ONLY = 0x01,
    DPM_SOP_CAB_TYPE_RX_SOP1_ONLY = 0x02,
    DPM_SOP_CAB_TYPE_RX_SOP2_ONLY = 0x04,
    DPM_SOP_CAB_TYPE_RX_SOP1_DBG_ONLY = 0x08,
    DPM_SOP_CAB_TYPE_RX_SOP2_DBG_ONLY = 0x10,
    DPM_SOP_CAB_TYPE_RX_HRST_ONLY = 0x20,
    DPM_SOP_CAB_TYPE_RX_CBLRST_ONLY = 0x40,
    DPM_SOP_CAB_TYPE_RX_SOP = 0x21, ///< SOP and Hard Reset
    DPM_SOP_CAB_TYPE_RX_SOP1 = 0x42, ///< SOP' and Cable Reset
    DPM_SOP_CAB_TYPE_RX_SOP2 = 0x44, ///< SOP" and Cable Reset
    DPM_SOP_CAB_TYPE_RX_SOP1_DBG = 0x4A, ///< SOP', SOP'DBG and Cable Reset
    DPM_SOP_CAB_TYPE_RX_SOP2_DBG = 0x4C, ///< SOP", SOP"DBG and Cable Reset
    DPM_SOP_CAB_TYPE_RX_ALL = 0x3F ///< ALL, without Cable reset
} DPM_SOP_CAB_TYPE_t;

typedef enum DPM_ROLE_CTRL_RP_VALUE_e
{
    DPM_ROLE_CTRL_RP_DEFAULT,
    DPM_ROLE_CTRL_RP_1P5A,
    DPM_ROLE_CTRL_RP_3A,
    DPM_ROLE_CTRL_RP_RESV
} DPM_ROLE_CTRL_RP_VALUE_t;

typedef enum DPM_ROLE_CTRL_CC_TYPE_e
{
    DPM_ROLE_CTRL_CC_RA,
    DPM_ROLE_CTRL_CC_RP,
    DPM_ROLE_CTRL_CC_RD,
    DPM_ROLE_CTRL_CC_OPEN
} DPM_ROLE_CTRL_CC_TYPE_t;

typedef enum DPM_CC_RX_SEL_e
{
    DPM_CC_RX_SEL_SINKING_PWR,
    DPM_CC_RX_SEL_PWR_NEUTRAL,
    DPM_CC_RX_SEL_SOURCING_PWR,
    DPM_CC_RX_SEL_VREF_CUT
} DPM_CC_RX_SEL_t;

typedef enum DPM_DEV_MODE_e
{
    DPM_DEV_MODE_SNK,
    DPM_DEV_MODE_SRC,
    DPM_DEV_MODE_DRP,
    DPM_DEV_MODE_CBL_PLUG,
    DPM_DEV_MODE_NO_PD_SNK,
    DPM_DEV_MODE_NO_PD_SRC,
    DPM_DEV_MODE_NO_PD_DRP,
    DMP_DEV_MODE_END
} DPM_DEV_MODE_t;

typedef enum DPM_PORT_STATE_e
{
    DPM_PORT_STATE_IDLE,
    DPM_PORT_STATE_CHARGE,
    DPM_PORT_STATE_DISCHARGE,
    DPM_PORT_STATE_INVALID
} DPM_PORT_STATE_t;

/* same as CURRENT_SRC_SUPPLY_TYPE_t */
typedef enum DPM_SOURCE_RP_e
{
    DPM_SOURCE_RP_OFF,
    DPM_SOURCE_RP_5V_0P5A,
    DPM_SOURCE_RP_5V_1P5A,
    DPM_SOURCE_RP_5V_3A,
    DPM_SOURCE_RP_END
} DPM_SOURCE_RP_t;

#define DPM_SOURCE_RP_SinkTxNG      (DPM_SOURCE_RP_5V_1P5A)
#define DPM_SOURCE_RP_SinkTxOk      (DPM_SOURCE_RP_5V_3A)

typedef struct DPM_PORT_INFO_s
{
    u32_t cable_detect_done:1;                  ///< Indicat cable detected
    u32_t not_type_c:1;                         ///< 
    u32_t current_pwr_mode:1;                   ///<
    u32_t dfp_mode:1;                           ///<
    u32_t ufp_mode:1;                           ///<
    u32_t vcon_is_on:1;                         ///<
    u32_t vcon_is_off:1;                        ///<
    u32_t source_cap_change:1;                  ///<
    u32_t req_identity_discov:1;                ///<
    u32_t req_svid_discov:1;                    ///<
    u32_t req_mode_discov:1;                    ///<
    u32_t req_mode_enter:1;                     ///<
    u32_t req_mode_exit:1;                      ///<
    u32_t default_pwr_mode:1;                   ///<
    u32_t request_can_be_met:1;                 ///<
    u32_t request_cant_be_met:1;                ///<
    u32_t request_could_be_met_later:1;         ///<
    u32_t power_supply_ready:1;                 ///<
    u32_t get_snk_cap_req:1;                    ///<
    u32_t goto_min_req:1;                       ///<
    u32_t vbus_at_vsafe5v:1;                    ///<
    u32_t dr_swp_req:1;                         ///<
    u32_t pr_swp_req:1;                         ///<
    u32_t get_src_cap_req:1;                    ///<
    u32_t vconn_swp_req:1;                      ///<
    u32_t req_attention_frm_ufp:1;              ///<
    u32_t contract_valid:1;                     ///<
    u32_t hard_reset_req:1;                     ///<
    u32_t pwr_snk_at_default:1;                 ///<
    u32_t response_received:1;                  ///<
    u32_t new_pwrlevel_req:1;                   ///<
    u32_t req_src_cap_update:1;                 ///<


    u32_t dr_swp_ok:1;                          ///<
    u32_t dr_swp_not_ok:1;                      ///<
    u32_t furthur_evaluate_drswp_is_needed:1;   ///<
    u32_t pr_swp_ok:1;                          ///<
    u32_t pr_swp_not_ok:1;                      ///<
    u32_t furthur_evaluate_prswp_is_needed:1;   ///<
    u32_t src_snk:1;                            ///<
    u32_t rd_asserted:1;                        ///<
    u32_t rp_asserted:1;                        ///<
    u32_t vcon_swp_not_ok:1;                    ///<
    u32_t vcon_swp_ok:1;                        ///<
    u32_t furthur_evaluate_vcswp_is_needed:1;   ///<
    u32_t mode_entered:1;                       ///<
    u32_t mode_enter_nak:1;                     ///<
    u32_t mode_exited:1;                        ///<
    u32_t cable_reset_req:1;                    ///<
    u32_t vdm_nak:1;                            ///<
    u32_t vdm_busy:1;                           ///<
    u32_t vdm_ack:1;                            ///<
    u32_t cable_plug:1;                         ///<
    u32_t msg_sop_type:3;                       ///<
    u32_t sop2_present:1;                       ///< read from VDM disc ident ack
    u32_t prs_req_rejected:1;                   ///<
    u32_t drs_req_rejected:1;                   ///< 
    u32_t vcs_req_rejected:1;                   ///< 
    u32_t pr_swp_requested_flag:1;              ///< 
    u32_t dr_swp_requested_flag:1;              ///< 
    u32_t vcon_swp_requested_flag:1;            ///< 
    u32_t vdm_disc_ident_requested_flag:1;      ///< 
    u32_t pps_disabled:1;                       ///< PPS is disabled
    

    u32_t resv3:3;                              ///<
    u32_t cbl_plug_detected:1;                  ///<
    u32_t orient_select:1;                      ///<
    u32_t disabled:1;                           ///<
    u32_t dead_battery:1;                       ///<
    u32_t tx_in_prog:1;                         ///<
    u32_t cc1_adc_rslt:12;                      ///<
    u32_t cc2_adc_rslt:12;                      ///<


    u32_t req_sop1_svid_discov:1;               ///<
    u32_t req_sop1_mode_discov:1;               ///<
    u32_t req_sop1_mode_enter:1;                ///<
    u32_t req_sop1_mode_exit:1;                 ///<
    u32_t req_sop2_svid_discov:1;               ///<
    u32_t req_sop2_mode_discov:1;               ///<
    u32_t req_sop2_mode_enter:1;                ///<
    u32_t req_sop2_mode_exit:1;                 ///<
    u32_t def_pwr_mode_configured:1;            ///<
    u32_t rx_src_cap_mismatch:1;                ///< mismatch source capability flag, sink mode
    u32_t rx_vdm_ack_modal_opr_supported:1;     ///< VDM responder modal operation supported flag 
    u32_t rx_vdm_ack_cable_vbus_current_cap:2;  ///< received VDM ACK from cable plug, VBUS current handling capability, 0: rsvd, 1: 3A, 2: 5A, 3: rsvd
    u32_t rx_vdm_req_mode_pos:4;                ///< received VDM INITIATOR request mode position
    u32_t req_spec_rev:2;                       ///< request specification revision
    u32_t pe_rxmsg_type:8;                      ///<
    u32_t pe_rxmsg_ind:1;                       ///<
    u32_t capture_mode_cc_configured:1;         ///< CC configured flag in capture mode
    u32_t src_ping_req:1;                       ///< Source port ping request
    u32_t alert_req:1;                          ///< Alert request
    u32_t vdm_disc_ident_request_again_flag:1;  ///< VDM Discovery identity request again flag


    u32_t curr_mode;                            ///< current modal operation


    u32_t rx_src_cap[MAX_DATA_OBJECT_NUM];      ///< received source capability, sink mode


    u32_t rx_src_cap_num:8;                     ///< received source capability number, sink mode
    u32_t rx_src_cap_max_power_index:8;         ///< received source capability maximal power index, sink mode
    u32_t rx_vdm_req_vid:16;                    ///< received VDM INITIATOR VID


    u32_t rx_src_cap_max_power;                 ///< received source capability maximal power, sink mode


    u32_t current_rdo;                          ///< received request data object


    u32_t rx_vdm_ack_vid:16;                    ///< received VDM ACK VID
    u32_t rx_vdm_ack_svid:16;                   ///< received VDM ACK SVID


    u32_t rx_vdm_ack_bcd_device:16;             ///< received VDM ACK BCD device
    u32_t rx_vdm_ack_prod_id:16;                ///< received VDM ACK Product ID


    u32_t rx_vdm_ack_tid;                       ///< received VDM ACK TID

#if PR_SWP_REQUEST_AUTO_ENABLED
    drv_timer_t pr_swp_request_timer;
#endif /* PR_SWP_REQUEST_AUTO_ENABLED */

    u32_t battery_present_capacity:16;  /* Battery's State of Charge (SoC), 0xFFFF = Battery's SOC unknown  */
    u32_t fixed_batteries:4;   /* Fixed Batteries, When Battery Status Change 
                                * bit set indicates which Fixed Batteries have 
                                * had a status change. B20 corresponds to 
                                * Battery 0 and B23 corresponds to Battery 3. */
    u32_t hot_swappable_batteries:4;    /* Hot Swappable Batteries, 
                                         * When Battery Status Change 
                                         * bit set indicates which Hot Swappable 
                                         * Batteries have had a status change. 
                                         * B16 corresponds to Battery 4 and 
                                         * B19 corresponds to Battery 7. */
    u32_t alert_type:8;                 /* Type of Current Alert 
                                             Bit Description
                                             0   Reserved and Shall be set to zero
                                             1   Battery Status Change
                                                 Event(Attach/Detach/charging/discharging/idle)
                                             2   OCP event when set (Source only, for Sink
                                                 Reserved and Shall be set to zero)
                                             3   OTP event when set
                                             4   Operating Condition Change when set
                                             5   Source Input Change Event when set
                                             6   OVP event when set (Sink only, for Source
                                                 Reserved and Shall be set to zero)
                                             7   Reserved and Shall be set to zero
                                         */

    u32_t req_country_info_code1:8;     /* First character of the Alpha-2 Country
                                         * Code defined by [ISO 3166]  
                                         */
    u32_t req_country_info_code2:8;     /* Second character of the Alpha-2 Country
                                         * Code defined by [ISO 3166]  
                                         */
    u32_t get_ext_status_req:1;         ///< Request extended status
    u32_t get_ext_src_cap_req:1;        ///< Request extended source capability
    u32_t get_ext_snk_cap_req:1;        ///< Request extended sink capability
    u32_t get_ext_mfr_req:1;            ///< Request extended manufacturer information
    u32_t get_ext_bat_status_req:1;     ///< Request extended battery status
    u32_t get_ext_bat_cap_req:1;        ///< Request extended battery capability
    u32_t get_ext_pps_status_req:1;     ///< Request extended PPS status
    u32_t get_ext_ctry_info_req:1;      ///< Request extended country info
    u32_t get_ext_ctry_codes_req:1;     ///< Request extended country codes
    u32_t partner_prod_type:3;          ///< partner product type
    u32_t frs_req:1;                    ///< fast role swap
    u32_t source_cap_5v_change_ibus_2p4a:1;         ///< source cap 5V change ibus to 2.4A
    u32_t source_ocp_flag:1;                        ///< source over current protection flag
    u32_t hrst_due_to_no_current_flag:1;    ///< hard reset due to no current flag
    u32_t port_state:2;                      ///< port state

    u32_t pps_output_voltage:16;        ///< Current output voltage for PPS
    u32_t pps_operating_current:16;     ///< Current operating current for PPS

    u32_t tx_src_cap_gt_3a_flag:1,      ///< Tx Source Capability Current greater than 3A flag
          vdm_disc_ident_requested_result:2,        ///< vdm_disc_ident_requested_result
          rx_ufp_vdm_ack_flag:1,        ///< Received UFP VDM ACK Flag
          rx_ufp_vdm_ack_modal_opr_supported:1, ///< VDM responder modal operation supported flag 
          ufp_partner_prod_type:3,
          otg_mode_flag:1,
          vsafe_5v_check_fail:1,
          vdm_resp_ignore:1,            ///< VDM responder ignore
          vbus_volt_set:16,
          reserved:5;                  ///< Reserved

    u32_t rx_ufp_vdm_ack_vid:16;        ///< Received UFP VDM ACK VID
    u32_t rx_ufp_vdm_ack_svid:16;       ///< Received UFP VDM ACK SVID


    u32_t rx_ufp_vdm_ack_bcd_device:16; ///< Received UFP VDM ACK BCD device
    u32_t rx_ufp_vdm_ack_prod_id:16;    ///< Received UFP VDM ACK Product ID


    u32_t rx_ufp_vdm_ack_tid;           ///< Received UFP VDM ACK TID
    
    u32_t rx_epr_mode_act_enter:1;      ///< Received  epr mode enter
    u32_t rx_epr_mode_act_enter_acknowledged:1;  ///< Received epr enter mode acknowledged
    u32_t rx_epr_mode_act_enter_succeeded:1;    ///< Received epr enter mode enter succeed
    u32_t rx_epr_mode_act_enter_failed:1;      ///< Received epr enter mode enter fail
    u32_t rx_epr_mode_act_exit:1;            ///< Received  epr mode exit
    u32_t rx_epr_mode_data_enter_fail_cause:8; ///< Received epr mode enter fail cause
    u32_t rx_req_epr_mode:1;                    ///< received snk request epr mode flag
    u32_t tx_epr_mode_data_enter_fail_cause:8; ///< src tx epr mode enter fail cause
    u32_t tx_epr_mode_msg_act:8;               ///< tx epr mode msg act
    u32_t epr_mode:1;                          ///< port in epr mode 
    u32_t resv1:1;

    u32_t rx_vdm_ack_cable_vbus_max_volt:2;///<received VDM ACK from cable plug,cable vbus max volt
    u32_t rx_vdm_ack_cable_epr_mode:1;     ///<received VDM ACK from cable plug, support epr mode
    u32_t src_obj_pos:4; 
    u32_t snk_epr_mode_req:1;
    u32_t epr_mode_exit_req:1;
    u32_t tx_ext_ctr_msg_type:8;
    u32_t rx_ext_ctr_msg_type:8;
    u32_t get_snk_cap_req_epr:1;
    u32_t get_src_cap_req_epr:1;
    u32_t chunk_router_rxmsg_ing:1;
    u32_t resv2:4;
    
} DPM_PORT_INFO_t;


typedef struct DPM_LPM_RESV_MEM_s 
{
    u32_t   pe_state:8;
    u32_t   current_pwr_mode:1;
    u32_t   dfp_mode:1;
    u32_t   default_pwr_mode:1;
    u32_t   modal_operation:1;
    u32_t   disc_ident_cnt:5;
    u32_t   pe_dfp_cbl_vdm_sop1_entered:1;
    u32_t   pe_dfp_cbl_vdm_sop1_cmplt:1;
    u32_t   cbl_plug_detected:1;
    u32_t   sop2_present:1;
    u32_t   pwr_changed:1;
    u32_t   src_obj_pos:3;
    u32_t   cable_detect_done:1;
    u32_t   tx_sop_msg_id:3; ///< transmit SOP message id
    u32_t   req_spec_rev:2;  ///< request specification revision
    u32_t   pps_disabled:1;

    u32_t   tx_sop1_msg_id:3; ///< transmit SOP' message id 
    u32_t   tx_sop2_msg_id:3; ///< transmit SOP" message id 
    u32_t   tx_sop1d_msg_id:3; ///< transmit SOP' debug message id 
    u32_t   tx_sop2d_msg_id:3; ///< transmit SOP" debug message id 
    u32_t   rx_sop_msg_id:3; ///< stored SOP message id 
    u32_t   rx_sop_msg_id_stored:1; ///< stored SOP message id flag
    u32_t   rx_sop1_msg_id:3; ///< stored SOP' message id 
    u32_t   rx_sop1_msg_id_stored:1; ///< stored SOP' message id flag
    u32_t   rx_sop2_msg_id:3; ///< stored SOP" message id 
    u32_t   rx_sop2_msg_id_stored:1; ///< stored SOP" message id flag
    u32_t   rx_sop1d_msg_id:3; ///< stored SOP' debug message id 
    u32_t   rx_sop1d_msg_id_stored:1; ///< stored SOP' debug message id flag
    u32_t   rx_sop2d_msg_id:3; ///< stored SOP" debug message id 
    u32_t   rx_sop2d_msg_id_stored:1; ///< stored SOP" debug message id flag

    u32_t   cc1_adc_rslt:12;
    u32_t   cc2_adc_rslt:12;
    u32_t   rx_src_cap_max_power:7;
    u32_t   rx_src_cap_mismatch:1;

    u32_t   curr_mode;

    u32_t   vbus_volt_set:16;
    u32_t   resv:16;
} DPM_LPM_RESV_MEM_t;

typedef struct DPM_BIST_TEST_DATA_s
{
    u32_t valid:1;
    u32_t len:7;
    u32_t reserved:24;
    u8_t test_data[DPM_BIST_TEST_DATA_SIZE];
} DPM_BIST_TEST_DATA_t;
#pragma pack()

/**  */
void dpm_cable_detect_done_set(u32_t flg);

/**  */
#define dpm_cable_detect_done_get() \
    (g_dpm_info.cable_detect_done)

/**  */
#define dpm_not_type_c_set(flg) \
    do { \
        g_dpm_info.not_type_c = (flg); \
    } while(0)

/**  */
#define dpm_not_type_c_get() \
    (g_dpm_info.not_type_c)

/**  */
#define dpm_current_pwr_mode_set(flg) \
    do { \
        g_dpm_info.current_pwr_mode = (flg); \
        DRV_REG_FIELD_SET(DPM_PRL_REG,PWR_ROLE,(flg)); \
    } while(0)

/**  */
#define dpm_current_pwr_mode_get() \
    (g_dpm_info.current_pwr_mode)

/**  */
#define dpm_dfp_mode_set(flg) \
    do { \
        g_dpm_info.dfp_mode = (flg); \
        DRV_REG_FIELD_SET(DPM_PRL_REG,DATA_ROLE,(flg)); \
    } while(0)

/**  */
#define dpm_dfp_mode_get() \
    (g_dpm_info.dfp_mode)

/**  */
#define dpm_ufp_mode_set(flg) \
    do { \
        g_dpm_info.ufp_mode = (flg); \
    } while(0)

/**  */
#define dpm_ufp_mode_get() \
    (g_dpm_info.ufp_mode)

/**  */
#define dpm_vcon_is_on_set(flg) \
    do { \
        g_dpm_info.vcon_is_on = (flg); \
    } while(0)

/**  */
#define dpm_vcon_is_on_get() \
    (g_dpm_info.vcon_is_on)

/**  */
#define dpm_vcon_is_off_set(flg) \
    do { \
        g_dpm_info.vcon_is_off = (flg); \
    } while(0)

/**  */
#define dpm_vcon_is_off_get() \
    (g_dpm_info.vcon_is_off)

/**  */
#define dpm_source_cap_change_set(flg) \
    do { \
        g_dpm_info.source_cap_change = (flg); \
    } while(0)

/**  */
#define dpm_source_cap_change_get() \
    (g_dpm_info.source_cap_change)

/**  */
#define dpm_req_identity_discov_set(flg) \
    do { \
        g_dpm_info.req_identity_discov = (flg); \
    } while(0)

/**  */
#define dpm_req_identity_discov_get() \
    (g_dpm_info.req_identity_discov)

/**  */
#define dpm_req_svid_discov_set(flg) \
    do { \
        g_dpm_info.req_svid_discov = (flg); \
    } while(0)

/**  */
#define dpm_req_svid_discov_get() \
    (g_dpm_info.req_svid_discov)

/**  */
#define dpm_req_mode_discov_set(flg) \
    do { \
        g_dpm_info.req_mode_discov = (flg); \
    } while(0)

/**  */
#define dpm_req_mode_discov_get() \
    (g_dpm_info.req_mode_discov)

/**  */
#define dpm_req_mode_enter_set(flg) \
    do { \
        g_dpm_info.req_mode_enter = (flg); \
    } while(0)

/**  */
#define dpm_req_mode_enter_get() \
    (g_dpm_info.req_mode_enter)

/**  */
#define dpm_req_mode_exit_set(flg) \
    do { \
        g_dpm_info.req_mode_exit = (flg); \
    } while(0)

/**  */
#define dpm_req_mode_exit_get() \
    (g_dpm_info.req_mode_exit)

/**  */
#define dpm_default_pwr_mode_set(flg) \
    do { \
        g_dpm_info.default_pwr_mode = (flg); \
    } while(0)

/**  */
#define dpm_default_pwr_mode_get() \
    (g_dpm_info.default_pwr_mode)

/**  */
#define dpm_request_can_be_met_set(flg) \
    do { \
        g_dpm_info.request_can_be_met = (flg); \
    } while(0)

/**  */
#define dpm_request_can_be_met_get() \
    (g_dpm_info.request_can_be_met)

/**  */
#define dpm_request_cant_be_met_set(flg) \
    do { \
        g_dpm_info.request_cant_be_met = (flg); \
    } while(0)

/**  */
#define dpm_request_cant_be_met_get() \
    (g_dpm_info.request_cant_be_met)

/**  */
#define dpm_request_could_be_met_later_set(flg) \
    do { \
        g_dpm_info.request_could_be_met_later = (flg); \
    } while(0)

/**  */
#define dpm_request_could_be_met_later_get() \
    (g_dpm_info.request_could_be_met_later)

/**  */
void dpm_power_supply_req();

#define dpm_snk_transit_to_new_power_req() \
    do { \
        usbpd_snk_transit_to_new_power_hook(); \
    } while(0)

/**  */
#define dpm_power_supply_ready_get() \
    (g_dpm_info.power_supply_ready)

/**  */
#define dpm_get_snk_cap_req_set(flg) \
    do { \
        g_dpm_info.get_snk_cap_req = (flg); \
    } while(0)

/**  */
#define dpm_get_snk_cap_req_get() \
    (g_dpm_info.get_snk_cap_req)

/**  */

/**  */
#define dpm_get_snk_cap_req_epr_set(flg) \
    do { \
        g_dpm_info.get_snk_cap_req_epr = (flg); \
    } while(0)

/**  */
#define dpm_get_snk_cap_req_epr_get() \
    (g_dpm_info.get_snk_cap_req_epr)

/**  */

/**  */
#define dpm_get_src_cap_req_epr_set(flg) \
    do { \
        g_dpm_info.get_src_cap_req_epr = (flg); \
    } while(0)

/**  */
#define dpm_get_src_cap_req_epr_get() \
    (g_dpm_info.get_src_cap_req_epr)

/**  */

#define dpm_goto_min_req_set(flg) \
    do { \
        g_dpm_info.goto_min_req = (flg); \
    } while(0)

/**  */
#define dpm_goto_min_req_get() \
    (g_dpm_info.goto_min_req)

/**  */
#define dpm_vbus_at_vsafe5v_set(flg) \
    do { \
        g_dpm_info.vbus_at_vsafe5v = (flg); \
    } while(0)

/**  */
#define dpm_vbus_at_vsafe5v_get() \
    (g_dpm_info.vbus_at_vsafe5v)


void dpm_drs_evaluate_req();
void dpm_drs_change_req();

/**  */
#define dpm_dr_swp_req_set(flg) \
    do { \
        g_dpm_info.dr_swp_req = (flg); \
    } while(0)

/**  */
#define dpm_dr_swp_req_get() \
    (g_dpm_info.dr_swp_req)

void dpm_prs_evaluate_req();
void dpm_prs_change_req(u32_t on);

/**  */
#define dpm_pr_swp_req_set(flg) \
    do { \
        g_dpm_info.pr_swp_req = (flg); \
    } while(0)

/**  */
#define dpm_pr_swp_req_get() \
    (g_dpm_info.pr_swp_req)



/**  */
#define dpm_prs_req_rejected_set(flg) \
    do { \
        g_dpm_info.prs_req_rejected = (flg); \
    } while(0)

/**  */
#define dpm_prs_req_rejected_get() \
    (g_dpm_info.prs_req_rejected)


/**  */
#define dpm_drs_req_rejected_set(flg) \
    do { \
        g_dpm_info.drs_req_rejected = (flg); \
    } while(0)

/**  */
#define dpm_drs_req_rejected_get() \
    (g_dpm_info.drs_req_rejected)


/**  */
#define dpm_vcs_req_rejected_set(flg) \
    do { \
        g_dpm_info.vcs_req_rejected = (flg); \
    } while(0)

/**  */
#define dpm_vcs_req_rejected_get() \
    (g_dpm_info.vcs_req_rejected)


/**  */
#define dpm_pr_swp_requested_flag_set(flg) \
    do { \
        g_dpm_info.pr_swp_requested_flag = (flg); \
    } while(0)

/**  */
#define dpm_pr_swp_requested_flag_get() \
    (g_dpm_info.pr_swp_requested_flag)


/**  */
#define dpm_dr_swp_requested_flag_set(flg) \
    do { \
        g_dpm_info.dr_swp_requested_flag = (flg); \
    } while(0)

/**  */
#define dpm_dr_swp_requested_flag_get() \
    (g_dpm_info.dr_swp_requested_flag)


/**  */
#define dpm_vcon_swp_requested_flag_set(flg) \
    do { \
        g_dpm_info.vcon_swp_requested_flag = (flg); \
    } while(0)

/**  */
#define dpm_vcon_swp_requested_flag_get() \
    (g_dpm_info.vcon_swp_requested_flag)


/**  */
#define dpm_vdm_disc_ident_requested_flag_set(flg) \
    do { \
        g_dpm_info.vdm_disc_ident_requested_flag = (flg); \
    } while(0)

/**  */
#define dpm_vdm_disc_ident_requested_flag_get() \
    (g_dpm_info.vdm_disc_ident_requested_flag)



/**  */
#define dpm_get_src_cap_req_set(flg) \
    do { \
        g_dpm_info.get_src_cap_req = (flg); \
    } while(0)

/**  */
#define dpm_get_src_cap_req_get() \
    (g_dpm_info.get_src_cap_req)

/**  */
#define dpm_vconn_swp_req_set(flg) \
    do { \
        g_dpm_info.vconn_swp_req = (flg); \
    } while(0)

/**  */
#define dpm_vconn_swp_req_get() \
    (g_dpm_info.vconn_swp_req)

/**  */
#define dpm_req_attention_frm_ufp_set(flg) \
    do { \
        g_dpm_info.req_attention_frm_ufp = (flg); \
    } while(0)

/**  */
#define dpm_req_attention_frm_ufp_get() \
    (g_dpm_info.req_attention_frm_ufp)

/**  */
#define dpm_contract_valid_set(flg) \
    do { \
        g_dpm_info.contract_valid = (flg); \
    } while(0)

/**  */
#define dpm_contract_valid_get() \
    (g_dpm_info.contract_valid)

/**  */
#define dpm_hard_reset_req_set(flg) \
    do { \
        g_dpm_info.hard_reset_req = (flg); \
    } while(0)

/**  */
#define dpm_hard_reset_req_get() \
    (g_dpm_info.hard_reset_req)

/**  */
#define dpm_pwr_snk_at_default_set(flg) \
    do { \
        g_dpm_info.pwr_snk_at_default = (flg); \
    } while(0)

/**  */
#define dpm_pwr_snk_at_default_get() \
    (g_dpm_info.pwr_snk_at_default)

/**  */
#define dpm_response_received_set(flg) \
    do { \
        g_dpm_info.response_received = (flg); \
    } while(0)

/**  */
#define dpm_response_received_get() \
    (g_dpm_info.response_received)

/**  */
#define dpm_new_pwrlevel_req_set(flg) \
    do { \
        g_dpm_info.new_pwrlevel_req = (flg); \
    } while(0)

/**  */
#define dpm_new_pwrlevel_req_get() \
    (g_dpm_info.new_pwrlevel_req)

/**  */
#define dpm_snk_epr_mode_req_set(flg) \
    do { \
        g_dpm_info.snk_epr_mode_req = (flg); \
    } while(0)

/**  */
#define dpm_snk_epr_mode_req_get() \
    (g_dpm_info.snk_epr_mode_req)

/**  */
#define dpm_epr_mode_exit_req_set(flg) \
    do { \
        g_dpm_info.epr_mode_exit_req = (flg); \
    } while(0)

/**  */
#define dpm_epr_mode_exit_req_get() \
    (g_dpm_info.epr_mode_exit_req)

/**  */
#define dpm_req_src_cap_update_set(flg) \
    do { \
        g_dpm_info.req_src_cap_update = (flg); \
    } while(0)

/**  */
#define dpm_req_src_cap_update_get() \
    (g_dpm_info.req_src_cap_update)

/**  */
#define dpm_dr_swp_ok_set(flg) \
    do { \
        g_dpm_info.dr_swp_ok = (flg); \
    } while(0)

/**  */
#define dpm_dr_swp_ok_get() \
    (g_dpm_info.dr_swp_ok)

/**  */
#define dpm_dr_swp_not_ok_set(flg) \
    do { \
        g_dpm_info.dr_swp_not_ok = (flg); \
    } while(0)

/**  */
#define dpm_dr_swp_not_ok_get() \
    (g_dpm_info.dr_swp_not_ok)

/**  */
#define dpm_furthur_evaluate_drswp_is_needed_set(flg) \
    do { \
        g_dpm_info.furthur_evaluate_drswp_is_needed = (flg); \
    } while(0)

/**  */
#define dpm_furthur_evaluate_drswp_is_needed_get() \
    (g_dpm_info.furthur_evaluate_drswp_is_needed)

/**  */
#define dpm_pr_swp_ok_set(flg) \
    do { \
        g_dpm_info.pr_swp_ok = (flg); \
    } while(0)

/**  */
#define dpm_pr_swp_ok_get() \
    (g_dpm_info.pr_swp_ok)

/**  */
#define dpm_pr_swp_not_ok_set(flg) \
    do { \
        g_dpm_info.pr_swp_not_ok = (flg); \
    } while(0)

/**  */
#define dpm_pr_swp_not_ok_get() \
    (g_dpm_info.pr_swp_not_ok)

/**  */
#define dpm_furthur_evaluate_prswp_is_needed_set(flg) \
    do { \
        g_dpm_info.furthur_evaluate_prswp_is_needed = (flg); \
    } while(0)

/**  */
#define dpm_furthur_evaluate_prswp_is_needed_get() \
    (g_dpm_info.furthur_evaluate_prswp_is_needed)

/**  */
#define dpm_src_snk_set(flg) \
    do { \
        g_dpm_info.src_snk = (flg); \
    } while(0)

/**  */
#define dpm_src_snk_get() \
    (g_dpm_info.src_snk)

/**  */
#define dpm_rd_asserted_get() \
    (g_dpm_info.rd_asserted)


/**  */
#define dpm_rp_asserted_get() \
    (g_dpm_info.rp_asserted)

/**  */
#define dpm_vcon_swp_not_ok_set(flg) \
    do { \
        g_dpm_info.vcon_swp_not_ok = (flg); \
    } while(0)

/**  */
#define dpm_vcon_swp_not_ok_get() \
    (g_dpm_info.vcon_swp_not_ok)

/**  */
#define dpm_vcon_swp_ok_set(flg) \
    do { \
        g_dpm_info.vcon_swp_ok = (flg); \
    } while(0)

/**  */
#define dpm_vcon_swp_ok_get() \
    (g_dpm_info.vcon_swp_ok)

/**  */
#define dpm_furthur_evaluate_vcswp_is_needed_set(flg) \
    do { \
        g_dpm_info.furthur_evaluate_vcswp_is_needed = (flg); \
    } while(0)

/**  */
#define dpm_furthur_evaluate_vcswp_is_needed_get() \
    (g_dpm_info.furthur_evaluate_vcswp_is_needed)

/**  */
#define dpm_mode_entered_set(flg) \
    do { \
        g_dpm_info.mode_entered = (flg); \
    } while(0)

/**  */
#define dpm_mode_entered_get() \
    (g_dpm_info.mode_entered)

/**  */
#define dpm_mode_enter_nak_set(flg) \
    do { \
        g_dpm_info.mode_enter_nak = (flg); \
    } while(0)

/**  */
#define dpm_mode_enter_nak_get() \
    (g_dpm_info.mode_enter_nak)

/**  */
#define dpm_mode_exited_set(flg) \
    do { \
        g_dpm_info.mode_exited = (flg); \
    } while(0)

/**  */
#define dpm_mode_exited_get() \
    (g_dpm_info.mode_exited)

/**  */
#define dpm_cable_plug_set(flg) \
    do { \
        g_dpm_info.cable_plug = (flg); \
        DRV_REG_FIELD_SET(DPM_PRL_REG,CABLE_PLUG,(flg)); \
    } while(0)

/**  */
#define dpm_cable_plug_get() \
    (g_dpm_info.cable_plug)

/**  */
#define dpm_cable_reset_req_set(flg) \
    do { \
        g_dpm_info.cable_reset_req = (flg); \
    } while(0)

/**  */
#define dpm_cable_reset_req_get() \
    (g_dpm_info.cable_reset_req)

/**  */
#define dpm_vdm_nak_set(flg) \
    do { \
        g_dpm_info.vdm_nak = (flg); \
    } while(0)

/**  */
#define dpm_vdm_nak_get() \
    (g_dpm_info.vdm_nak)

/**  */
#define dpm_vdm_busy_set(flg) \
    do { \
        g_dpm_info.vdm_busy = (flg); \
    } while(0)

/**  */
#define dpm_vdm_busy_get() \
    (g_dpm_info.vdm_busy)

/**  */
#define dpm_vdm_ack_set(flg) \
    do { \
        g_dpm_info.vdm_ack = (flg); \
    } while(0)

/**  */
#define dpm_vdm_ack_get() \
    (g_dpm_info.vdm_ack)

/**  */
#define dpm_vdm_resp_ignore_set(flg) \
    do { \
        g_dpm_info.vdm_resp_ignore = (flg); \
    } while(0)

#define dpm_vdm_resp_ignore_get() \
    (g_dpm_info.vdm_resp_ignore)

/**  */
#define dpm_pe_rxmsg_ind_set(flg) \
    do { \
        g_dpm_info.pe_rxmsg_ind = (flg); \
    } while(0)

/**  */
#define dpm_pe_rxmsg_ind_get() \
    (g_dpm_info.pe_rxmsg_ind)

/**  */
#define dpm_chunk_router_rxmsg_ind_set(flg) \
    do { \
        g_dpm_info.chunk_router_rxmsg_ing = (flg); \
    } while(0)

/**  */
#define dpm_chunk_router_rxmsg_ind_get() \
    (g_dpm_info.chunk_router_rxmsg_ing)

/**  */
#define dpm_pe_rxmsg_type_set(flg) \
    do { \
        g_dpm_info.pe_rxmsg_type = (flg); \
    } while(0)

/**  */
#define dpm_pe_rxmsg_type_get() \
    (g_dpm_info.pe_rxmsg_type)


/**  */
#define dpm_src_obj_pos_set(flg) \
    do { \
        g_dpm_info.src_obj_pos = (flg); \
    } while(0)

/**  */
#define dpm_src_obj_pos_get() \
    (g_dpm_info.src_obj_pos)

/**  */
#define dpm_msg_sop_type_set(flg) \
    do { \
        g_dpm_info.msg_sop_type = (flg); \
    } while(0)

/**  */
#define dpm_msg_sop_type_get() \
    (g_dpm_info.msg_sop_type)


/**  */
#define dpm_cbl_plug_detected_get() \
    (g_dpm_info.cbl_plug_detected)

/**  */
#define dpm_cbl_plug_detected_set(flg) \
    do { \
        g_dpm_info.cbl_plug_detected = (flg); \
    } while(0)


/**  */
#define dpm_orient_select_get() \
    (g_dpm_info.orient_select)

/**  */
#define dpm_orient_select_set(flg) \
    do { \
        g_dpm_info.orient_select = (flg); \
        DRV_REG_FIELD_SET(DPM_REG_1,ORIENT_SELECT,(flg)); \
    } while(0)


/**  */
#define dpm_curr_mode_set(flg) \
    do { \
        g_dpm_info.curr_mode = (flg); \
    } while(0)

/**  */
#define dpm_curr_mode_get() \
    (g_dpm_info.curr_mode)

/**  */
#define dpm_req_epr_mode_flag_set(flg) \
    do { \
        g_dpm_info.rx_req_epr_mode = (flg); \
    } while(0)

/**  */
#define dpm_req_epr_mode_flag_get() \
    (g_dpm_info.rx_req_epr_mode)

/**  */
#define dpm_rx_ext_ctr_msg_type_set(flg) \
    do { \
        g_dpm_info.rx_ext_ctr_msg_type = (flg); \
    } while(0)

/**  */
#define dpm_rx_ext_ctr_msg_type_get() \
    (g_dpm_info.rx_ext_ctr_msg_type)

/**  */
#define dpm_tx_ext_ctr_msg_type_set(flg) \
    do { \
        g_dpm_info.tx_ext_ctr_msg_type = (flg); \
    } while(0)

/**  */
#define dpm_tx_ext_ctr_msg_type_get() \
    (g_dpm_info.tx_ext_ctr_msg_type)

void dpm_port_init();
status_t dpm_port_role_update();

void dpm_vcs_evaluate_req();
void dpm_vconn_change_req(u32_t on);

#define dpm_vcon_detected()     usbpd_cfg_port_vconn_detected_get()

bool_t dpm_vbus_detected();


#define dpm_vbus_source_en_get() \
    (usbpd_hook_with_return(src_vbus_en))

#define dpm_vbus_source_en_set(flg) \
    do { \
        usbpd_hook(src_vbus_en,flg); \
    } while(0)

status_t dpm_sop_cbl_type_set(u32_t type);
u32_t dpm_sop_cbl_type_get();


/**  */
#define dpm_port_disabled_set(flg) \
    do { \
        g_dpm_info.disabled = (flg); \
    } while(0)

/**  */
#define dpm_port_disabled_get() \
    (g_dpm_info.disabled)

/**  */
#define dpm_port_dead_battery_set(flg) \
    do { \
        g_dpm_info.dead_battery = (flg); \
    } while(0)

/**  */
#define dpm_port_dead_battery_get() \
    (g_dpm_info.dead_battery)


/**  */
#define dpm_cc1_adc_rslt_set(v) \
    do { \
        g_dpm_info.cc1_adc_rslt = (v); \
    } while(0)

/**  */
#define dpm_cc1_adc_rslt_get() \
    (g_dpm_info.cc1_adc_rslt)

/**  */
#define dpm_cc2_adc_rslt_set(v) \
    do { \
        g_dpm_info.cc2_adc_rslt = (v); \
    } while(0)

/**  */
#define dpm_cc2_adc_rslt_get() \
    (g_dpm_info.cc2_adc_rslt)

/**  */
#define dpm_rx_epr_enter_msg_set(v) \
    do { \
        g_dpm_info.rx_epr_mode_act_enter = (v); \
    } while(0)

/**  */
#define dpm_rx_epr_enter_msg_get() \
    (g_dpm_info.rx_epr_mode_act_enter)


/**  */
#define dpm_rx_epr_acknowledged_msg_set(v) \
    do { \
        g_dpm_info.rx_epr_mode_act_enter_acknowledged = (v); \
    } while(0)

/**  */
#define dpm_rx_epr_acknowledged_msg_get() \
    (g_dpm_info.rx_epr_mode_act_enter_acknowledged)

/**  */
#define dpm_rx_epr_succeed_msg_set(v) \
    do { \
        g_dpm_info.rx_epr_mode_act_enter_succeeded = (v); \
    } while(0)

/**  */
#define dpm_rx_epr_succeed_msg_get() \
    (g_dpm_info.rx_epr_mode_act_enter_succeeded)

/**  */
#define dpm_rx_epr_fail_msg_set(v) \
    do { \
        g_dpm_info.rx_epr_mode_act_enter_failed = (v); \
    } while(0)

/**  */
#define dpm_rx_epr_fail_msg_get() \
    (g_dpm_info.rx_epr_mode_act_enter_failed)


/**  */
#define dpm_rx_epr_exit_msg_set(v) \
    do { \
        g_dpm_info.rx_epr_mode_act_exit = (v); \
    } while(0)

/**  */
#define dpm_rx_epr_exit_msg_get() \
    (g_dpm_info.rx_epr_mode_act_exit)


/**  */
#define dpm_rx_epr_enter_fail_cause_set(v) \
    do { \
        g_dpm_info.rx_epr_mode_data_enter_fail_cause = (v); \
    } while(0)

/**  */
#define dpm_rx_epr_enter_fail_cause_get() \
    (g_dpm_info.rx_epr_mode_data_enter_fail_cause)


void dpm_rd_asserted_req();
void dpm_rp_asserted_req();
void dpm_port_reset();
void dpm_rp_rd_clear();
void dpm_rp_set(DPM_SOURCE_RP_t rp_type);

/** Set VDM SOP" controller present  */
#define dpm_vdm_sop2_present_set(en) \
    do { \
        g_dpm_info.sop2_present = en; \
    } while(0)

/** Get VDM SOP" controller present */
#define dpm_vdm_sop2_present_get() \
    (g_dpm_info.sop2_present)

bool_t dpm_on_sleep_handler(void);
bool_t dpm_on_wakeup_handler(void);


/** Set DPM in tx progress flag */
#define dpm_tx_in_prog_set(flg) \
    do { \
        g_dpm_info.tx_in_prog = flg; \
    } while(0)

/** Get DPM in tx progress flag */
#define dpm_tx_in_prog_get() \
    (g_dpm_info.tx_in_prog)


/**  */
#define dpm_req_sop1_svid_discov_set(flg) \
    do { \
        g_dpm_info.req_sop1_svid_discov = (flg); \
    } while(0)

/**  */
#define dpm_req_sop1_svid_discov_get() \
    (g_dpm_info.req_sop1_svid_discov)

/**  */
#define dpm_req_sop1_mode_discov_set(flg) \
    do { \
        g_dpm_info.req_sop1_mode_discov = (flg); \
    } while(0)

/**  */
#define dpm_req_sop1_mode_discov_get() \
    (g_dpm_info.req_sop1_mode_discov)

/**  */
#define dpm_req_sop1_mode_enter_set(flg) \
    do { \
        g_dpm_info.req_sop1_mode_enter = (flg); \
    } while(0)

/**  */
#define dpm_req_sop1_mode_enter_get() \
    (g_dpm_info.req_sop1_mode_enter)

/**  */
#define dpm_req_sop1_mode_exit_set(flg) \
    do { \
        g_dpm_info.req_sop1_mode_exit = (flg); \
    } while(0)

/**  */
#define dpm_req_sop1_mode_exit_get() \
    (g_dpm_info.req_sop1_mode_exit)


/**  */
#define dpm_req_sop2_svid_discov_set(flg) \
    do { \
        g_dpm_info.req_sop2_svid_discov = (flg); \
    } while(0)

/**  */
#define dpm_req_sop2_svid_discov_get() \
    (g_dpm_info.req_sop2_svid_discov)

/**  */
#define dpm_req_sop2_mode_discov_set(flg) \
    do { \
        g_dpm_info.req_sop2_mode_discov = (flg); \
    } while(0)

/**  */
#define dpm_req_sop2_mode_discov_get() \
    (g_dpm_info.req_sop2_mode_discov)

/**  */
#define dpm_req_sop2_mode_enter_set(flg) \
    do { \
        g_dpm_info.req_sop2_mode_enter = (flg); \
    } while(0)

/**  */
#define dpm_req_sop2_mode_enter_get() \
    (g_dpm_info.req_sop2_mode_enter)

/**  */
#define dpm_req_sop2_mode_exit_set(flg) \
    do { \
        g_dpm_info.req_sop2_mode_exit = (flg); \
    } while(0)

/**  */
#define dpm_req_sop2_mode_exit_get() \
    (g_dpm_info.req_sop2_mode_exit)


/**  */
#define dpm_def_pwr_mode_configured_set(flg) \
    do { \
        g_dpm_info.def_pwr_mode_configured = (flg); \
    } while(0)

/**  */
#define dpm_def_pwr_mode_configured_get() \
    (g_dpm_info.def_pwr_mode_configured)


/** DPM bist mode enable */
#define dpm_bist_mode_en(flg) \
    do { \
        DRV_REG_FIELD_SET(DPM_REG_1,BIST_MODE,(flg)); \
    } while(0)

#if PE_BIST_CARRIER_MODE2_ENABLED
/** DPM bist carrier mode 2 request */
void dpm_bist_carrier_mode2_req(u32_t sop_type);

/** DPM bist test data request */
void dpm_bist_test_data_req(u8_t *data_buf, u32_t len, u32_t sop_type);

/** Get DPM bist test data */
u8_t dpm_bist_test_data_get(volatile u8_t *data_buf);
#endif /* PE_BIST_CARRIER_MODE2_ENABLED */


/** Get rx source capability mismatch flag */
#define dpm_rx_src_cap_mismatch_get() \
    (g_dpm_info.rx_src_cap_mismatch)

/** Set rx source capability mismatch flag */
#define dpm_rx_src_cap_mismatch_set(flg) \
    do { \
        g_dpm_info.rx_src_cap_mismatch=(flg); \
    } while(0)


/** Get rx VDM ACK modal operation supported flag */
#define dpm_rx_vdm_ack_modal_opr_supported_get() \
    (g_dpm_info.rx_vdm_ack_modal_opr_supported)

/** Set rx VDM ACK modal operation supported flag */
#define dpm_rx_vdm_ack_modal_opr_supported_set(flg) \
    do { \
        g_dpm_info.rx_vdm_ack_modal_opr_supported=flg; \
    } while(0)


/** Get rx VDM ACK cable VBUS current capability flag */
#define dpm_rx_vdm_ack_cable_vbus_curr_cap_get() \
    (g_dpm_info.rx_vdm_ack_cable_vbus_current_cap)

/** Set rx VDM ACK cable VBUS current capability flag */
#define dpm_rx_vdm_ack_cable_vbus_curr_cap_set(flg) \
    do { \
        g_dpm_info.rx_vdm_ack_cable_vbus_current_cap=flg; \
    } while(0)

 /** Get rx VDM ACK cable VBUS volt capability flag */
#define dpm_rx_vdm_ack_cable_vbus_volt_max_get() \
    (g_dpm_info.rx_vdm_ack_cable_vbus_max_volt)
    
/** Set rx VDM ACK cable VBUS volt capability flag */
#define dpm_rx_vdm_ack_cable_volt_max_set(flg) \
    do { \
        g_dpm_info.rx_vdm_ack_cable_vbus_max_volt=flg; \
    } while(0)

/** Get rx VDM ACK cable epr mode flag */
#define dpm_rx_vdm_ack_cable_epr_mode_get() \
    (g_dpm_info.rx_vdm_ack_cable_epr_mode)
        
/** Set rx VDM ACK cable epr mode flag */
#define dpm_rx_vdm_ack_cable_epr_mode_set(flg) \
    do { \
        g_dpm_info.rx_vdm_ack_cable_epr_mode=flg; \
    } while(0)

/** Get rx VDM Initiator request mode position */
#define dpm_rx_vdm_req_mode_pos_get() \
    (g_dpm_info.rx_vdm_req_mode_pos)

/** Set rx VDM Initiator request mode position */
#define dpm_rx_vdm_req_mode_pos_set(val) \
    do { \
        g_dpm_info.rx_vdm_req_mode_pos=val; \
    } while(0)


/** Get request specification revision */
#define dpm_req_spec_rev_get() \
    (g_dpm_info.req_spec_rev)

/** Set request specification revision */
#if 0  /* modified by James Gan - 2019-11-07 */
#define dpm_req_spec_rev_set(val) \
    do { \
        g_dpm_info.req_spec_rev=val; \
    } while(0)
#else
void dpm_req_spec_rev_set(u32_t rev);
#endif /* #if 0 */


/** Get PPS disable state */
#define dpm_pps_disabled_get() \
    (g_dpm_info.pps_disabled)

/** Set PPS disable */
#define dpm_pps_disabled_set(val) \
    do { \
        g_dpm_info.pps_disabled=val; \
    } while(0)


/** Get capture mode cc configured flag */
#define dpm_capture_mode_cc_configured_get() \
    (g_dpm_info.capture_mode_cc_configured)

/** Set capture mode cc configured flag */
#define dpm_capture_mode_cc_configured_set(val) \
    do { \
        g_dpm_info.capture_mode_cc_configured=val; \
    } while(0)


/** Get src ping request flag */
#define dpm_src_ping_req_get() \
    (g_dpm_info.src_ping_req)

/** Set src ping request flag */
#define dpm_src_ping_req_set(val) \
    do { \
        g_dpm_info.src_ping_req=val; \
    } while(0)


/** Get alert request flag */
#define dpm_alert_req_get() \
    (g_dpm_info.alert_req)

/** Set alert request flag */
#define dpm_alert_req_set(val) \
    do { \
        g_dpm_info.alert_req=val; \
    } while(0)


/** VDM Discovery identity request again flag */
#define dpm_vdm_disc_ident_request_again_flag_get() \
    (g_dpm_info.vdm_disc_ident_request_again_flag)

/** VDM Discovery identity request again flag */
#define dpm_vdm_disc_ident_request_again_flag_set(flg) \
    do { \
        g_dpm_info.vdm_disc_ident_request_again_flag = (flg); \
    } while(0)


/** Get rx source capability number */
#define dpm_rx_src_cap_num_get() \
    (g_dpm_info.rx_src_cap_num)

/** Set rx source capability number */
#define dpm_rx_src_cap_num_set(v) \
    do { \
        g_dpm_info.rx_src_cap_num=(v); \
    } while(0)


/** Get rx source capability data object pointer */
#define dpm_rx_src_cap_object_get(idx) \
    (&(g_dpm_info.rx_src_cap[idx]))

/** Get rx source capability data object */
#define dpm_rx_src_cap_object_data_get(idx) \
    (g_dpm_info.rx_src_cap[idx])

/** Set rx source capability data object, v is u32_t type */
#define dpm_rx_src_cap_object_set(idx,v) \
    do { \
        g_dpm_info.rx_src_cap[idx]=(u32_t)(v); \
    } while(0)


/** Get rx source capability maximal power index */
#define dpm_rx_src_cap_max_power_index_get() \
    (g_dpm_info.rx_src_cap_max_power_index)

/** Set rx source capability maximal power index */
#define dpm_rx_src_cap_max_power_index_set(v) \
    do { \
        g_dpm_info.rx_src_cap_max_power_index=(v); \
    } while(0)


/** Get rx source capability maximal power value */
#define dpm_rx_src_cap_max_power_get() \
    (g_dpm_info.rx_src_cap_max_power)

/** Set rx source capability maximal power value */
#define dpm_rx_src_cap_max_power_set(v) \
    do { \
        g_dpm_info.rx_src_cap_max_power=(v); \
    } while(0)


/** Get rx source capability supply type */
#define dpm_rx_src_cap_supply_type_get(idx) \
    (((UPD_DATA_MSG_SOURCE_CAP_FIXED_SUPPLY_t *)(&(g_dpm_info.rx_src_cap[idx])))->supply_type)

/** Get rx source capability operating voltage */
#define dpm_rx_src_cap_opr_volt_get(idx) \
    (((UPD_DATA_MSG_SOURCE_CAP_FIXED_SUPPLY_t *)(&(g_dpm_info.rx_src_cap[idx])))->volt * VOLTAGE_DIV)

#define dpm_rx_src_cap_opr_volt_raw_get(idx) \
    (((UPD_DATA_MSG_SOURCE_CAP_FIXED_SUPPLY_t *)(&(g_dpm_info.rx_src_cap[idx])))->volt)

/** Get rx source capability maximal operating current */
#define dpm_rx_src_cap_max_curr_get(idx) \
    (((UPD_DATA_MSG_SOURCE_CAP_FIXED_SUPPLY_t *)(&(g_dpm_info.rx_src_cap[idx])))->max_curr * CURRENT_DIV)


/** Get rx PPS source capability maximal voltage */
#define dpm_rx_src_cap_pps_max_volt_get(idx) \
    (((UPD_DATA_MSG_SOURCE_CAP_PPS_APDU_t *)(&(g_dpm_info.rx_src_cap[idx])))->max_volt * VOLTAGE_PPS_DIV)

/** Get rx PPS source capability minimal voltage */
#define dpm_rx_src_cap_pps_min_volt_get(idx) \
    (((UPD_DATA_MSG_SOURCE_CAP_PPS_APDU_t *)(&(g_dpm_info.rx_src_cap[idx])))->min_volt * VOLTAGE_PPS_DIV)

/** Get rx PPS source capability raw maximal voltage */
#define dpm_rx_src_cap_pps_max_volt_raw_get(idx) \
    (((UPD_DATA_MSG_SOURCE_CAP_PPS_APDU_t *)(&(g_dpm_info.rx_src_cap[idx])))->max_volt)

/** Get rx PPS source capability raw minimal voltage */
#define dpm_rx_src_cap_pps_min_volt_raw_get(idx) \
    (((UPD_DATA_MSG_SOURCE_CAP_PPS_APDU_t *)(&(g_dpm_info.rx_src_cap[idx])))->min_volt)

/** Get rx source capability pps mode */
#define dpm_rx_src_cap_pps_mode_get(idx) \
    (((UPD_DATA_MSG_SOURCE_CAP_PPS_APDU_t *)(&(g_dpm_info.rx_src_cap[idx])))->pps)

/** Get rx source capability maximal operating current */
#define dpm_rx_src_cap_pps_max_curr_get(idx) \
    (((UPD_DATA_MSG_SOURCE_CAP_PPS_APDU_t *)(&(g_dpm_info.rx_src_cap[idx])))->max_curr * CURRENT_PPS_DIV)


/** Get rx AVS source capability maximal voltage */
#define dpm_rx_src_cap_avs_max_volt_get(idx) \
    (((UPD_DATA_MSG_SOURCE_CAP_AVS_APDU_t *)(&(g_dpm_info.rx_src_cap[idx])))->max_volt * VOLTAGE_PPS_DIV)

/** Get rx AVS source capability minimal voltage */
#define dpm_rx_src_cap_avs_min_volt_get(idx) \
    (((UPD_DATA_MSG_SOURCE_CAP_AVS_APDU_t *)(&(g_dpm_info.rx_src_cap[idx])))->min_volt * VOLTAGE_PPS_DIV)

/** Get rx AVS source capability raw minimal voltage */
#define dpm_rx_src_cap_avs_min_volt_raw_get(idx) \
    (((UPD_DATA_MSG_SOURCE_CAP_AVS_APDU_t *)(&(g_dpm_info.rx_src_cap[idx])))->min_volt)

/** Get rx AVS source capability raw maximal voltage */
#define dpm_rx_src_cap_avs_max_volt_raw_get(idx) \
    (((UPD_DATA_MSG_SOURCE_CAP_AVS_APDU_t *)(&(g_dpm_info.rx_src_cap[idx])))->max_volt)

/** Get rx AVS PDP */
#define dpm_rx_src_cap_avs_pdp_get(idx) \
    (((UPD_DATA_MSG_SOURCE_CAP_AVS_APDU_t *)(&(g_dpm_info.rx_src_cap[idx])))->pdp)

/** Get current request data object pointer */
#define dpm_current_rdo_get() \
    (&(g_dpm_info.current_rdo))

/** Set current request data object */
#define dpm_current_rdo_set(v) \
    do { \
        g_dpm_info.current_rdo=(u32_t)(v); \
    } while(0)


/** Get rx VDM Initiator VID */
#define dpm_rx_vdm_req_vid_get() \
    (g_dpm_info.rx_vdm_req_vid)

/** Set rx VDM Initiator VID */
#define dpm_rx_vdm_req_vid_set(val) \
    do { \
        g_dpm_info.rx_vdm_req_vid=val; \
    } while(0)


/** Get rx VDM ACK VID */
#define dpm_rx_vdm_ack_vid_get() \
    (g_dpm_info.rx_vdm_ack_vid)

/** Set rx VDM ACK VID */
#define dpm_rx_vdm_ack_vid_set(val) \
    do { \
        g_dpm_info.rx_vdm_ack_vid=val; \
    } while(0)


/** Get rx VDM ACK SVID */
#define dpm_rx_vdm_ack_svid_get() \
    (g_dpm_info.rx_vdm_ack_svid)

/** Set rx VDM ACK SVID */
#define dpm_rx_vdm_ack_svid_set(val) \
    do { \
        g_dpm_info.rx_vdm_ack_svid=val; \
    } while(0)


/** Get rx VDM ACK BCD device */
#define dpm_rx_vdm_ack_bcd_device_get() \
    (g_dpm_info.rx_vdm_ack_bcd_device)

/** Set rx VDM ACK BCD device */
#define dpm_rx_vdm_ack_bcd_device_set(val) \
    do { \
        g_dpm_info.rx_vdm_ack_bcd_device=val; \
    } while(0)


/** Get rx VDM ACK Product ID */
#define dpm_rx_vdm_ack_prod_id_get() \
    (g_dpm_info.rx_vdm_ack_prod_id)

/** Set rx VDM ACK Product ID */
#define dpm_rx_vdm_ack_prod_id_set(val) \
    do { \
        g_dpm_info.rx_vdm_ack_prod_id=val; \
    } while(0)


/** Get rx VDM ACK Test ID */
#define dpm_rx_vdm_ack_tid_get() \
    (g_dpm_info.rx_vdm_ack_tid)

/** Set rx VDM ACK Test ID */
#define dpm_rx_vdm_ack_tid_set(val) \
    do { \
        g_dpm_info.rx_vdm_ack_tid=val; \
    } while(0)



/** Get battery present capacity, 0xFFFF = Battery's SOC unknown */
#define dpm_battery_present_capacity_get() \
    (g_dpm_info.battery_present_capacity)

/** Set battery present capacity, 0xFFFF = Battery's SOC unknown */
#define dpm_battery_present_capacity_set(val) \
    do { \
        g_dpm_info.battery_present_capacity=val; \
    } while(0)




/** Get alert fixed_batteries */
#define dpm_alert_fixed_batteries_get() \
    (g_dpm_info.fixed_batteries)

/** Set alert fixed_batteries */
#define dpm_alert_fixed_batteries_set(val) \
    do { \
        g_dpm_info.fixed_batteries=val; \
    } while(0)



/** Get alert type */
#define dpm_alert_hot_swappable_batteries_get() \
    (g_dpm_info.hot_swappable_batteries)

/** Set alert type */
#define dpm_alert_hot_swappable_batteries_set(val) \
    do { \
        g_dpm_info.hot_swappable_batteries=val; \
    } while(0)


/** Get alert type */
#define dpm_alert_type_get() \
    (g_dpm_info.alert_type)

/** Set alert type */
#define dpm_alert_type_set(val) \
    do { \
        g_dpm_info.alert_type=val; \
    } while(0)



/** Get the code1 for getting country info */
#define dpm_req_country_info_code1_get() \
    (g_dpm_info.req_country_info_code1)

/** Set the code1 for getting country info */
#define dpm_req_country_info_code1_set(val) \
    do { \
        g_dpm_info.req_country_info_code1=val; \
    } while(0)



/** Get the code2 for getting country info */
#define dpm_req_country_info_code2_get() \
    (g_dpm_info.req_country_info_code2)

/** Set the code2 for getting country info */
#define dpm_req_country_info_code2_set(val) \
    do { \
        g_dpm_info.req_country_info_code2=val; \
    } while(0)



/** Get the extended status request flag */
#define dpm_get_ext_status_req_get() \
    (g_dpm_info.get_ext_status_req)

/** Set the extended status request flag  */
#define dpm_get_ext_status_req_set(val) \
    do { \
        g_dpm_info.get_ext_status_req=val; \
    } while(0)



/** Get the extended source capability request flag */
#define dpm_get_ext_src_cap_req_get() \
    (g_dpm_info.get_ext_src_cap_req)

/** Set the extended source capability request flag  */
#define dpm_get_ext_src_cap_req_set(val) \
    do { \
        g_dpm_info.get_ext_src_cap_req=val; \
    } while(0)



/** Get the extended sink capability request flag */
#define dpm_get_ext_snk_cap_req_get() \
    (g_dpm_info.get_ext_snk_cap_req)

/** Set the extended sink capability request flag  */
#define dpm_get_ext_snk_cap_req_set(val) \
    do { \
        g_dpm_info.get_ext_snk_cap_req=val; \
    } while(0)



/** Get the extended manufacturer info request flag */
#define dpm_get_ext_mfr_req_get() \
    (g_dpm_info.get_ext_mfr_req)

/** Set the extended manufacturer info request flag  */
#define dpm_get_ext_mfr_req_set(val) \
    do { \
        g_dpm_info.get_ext_mfr_req=val; \
    } while(0)



/** Get the extended battery status request flag */
#define dpm_get_ext_bat_status_req_get() \
    (g_dpm_info.get_ext_bat_status_req)

/** Set the extended battery status request flag  */
#define dpm_get_ext_bat_status_req_set(val) \
    do { \
        g_dpm_info.get_ext_bat_status_req=val; \
    } while(0)



/** Get the extended battery capability request flag */
#define dpm_get_ext_bat_cap_req_get() \
    (g_dpm_info.get_ext_bat_cap_req)

/** Set the extended batter capability request flag  */
#define dpm_get_ext_bat_cap_req_set(val) \
    do { \
        g_dpm_info.get_ext_bat_cap_req=val; \
    } while(0)



/** Get the extended PPS status request flag */
#define dpm_get_ext_pps_status_req_get() \
    (g_dpm_info.get_ext_pps_status_req)

/** Set the extended PPS status request flag  */
#define dpm_get_ext_pps_status_req_set(val) \
    do { \
        g_dpm_info.get_ext_pps_status_req=val; \
    } while(0)




/** Get the extended country info request flag */
#define dpm_get_ext_ctry_info_req_get() \
    (g_dpm_info.get_ext_ctry_info_req)

/** Set the extended country info request flag  */
#define dpm_get_ext_ctry_info_req_set(val) \
    do { \
        g_dpm_info.get_ext_ctry_info_req=val; \
    } while(0)


/** Get the extended country codes request flag */
#define dpm_get_ext_ctry_codes_req_get() \
    (g_dpm_info.get_ext_ctry_codes_req)

/** Set the extended country codes request flag  */
#define dpm_get_ext_ctry_codes_req_set(val) \
    do { \
        g_dpm_info.get_ext_ctry_codes_req=val; \
    } while(0)




/** Get the PPS output voltage */
#define dpm_pps_output_voltage_get() \
    (g_dpm_info.pps_output_voltage)

/** Set the PPS output voltage  */
#define dpm_pps_output_voltage_set(val) \
    do { \
        g_dpm_info.pps_output_voltage=val; \
    } while(0)




/** Get the PPS operating current */
#define dpm_pps_operating_current_get() \
    (g_dpm_info.pps_operating_current)

/** Set the PPS operating current  */
#define dpm_pps_operating_current_set(val) \
    do { \
        g_dpm_info.pps_operating_current=val; \
    } while(0)




/** Get Tx Source Capability Current greater than 3A flag */
#define dpm_tx_src_cap_gt_3a_flag_get() \
    (g_dpm_info.tx_src_cap_gt_3a_flag)

/** Set Tx Source Capability Current greater than 3A flag  */
#define dpm_tx_src_cap_gt_3a_flag_set(val) \
    do { \
        g_dpm_info.tx_src_cap_gt_3a_flag=val; \
    } while(0)




/** Get VDM discovery identity request result */
#define dpm_vdm_disc_ident_requested_result_get() \
    (g_dpm_info.vdm_disc_ident_requested_result)

/** Set VDM discovery identity request result  */
#define dpm_vdm_disc_ident_requested_result_set(val) \
    do { \
        g_dpm_info.vdm_disc_ident_requested_result=val; \
    } while(0)





/** Get UFP Received VDM ACK flag */
#define dpm_rx_ufp_vdm_ack_flag_get() \
    (g_dpm_info.rx_ufp_vdm_ack_flag)

/** Set UFP Received VDM ACK flag  */
#define dpm_rx_ufp_vdm_ack_flag_set(val) \
    do { \
        g_dpm_info.rx_ufp_vdm_ack_flag=val; \
    } while(0)





/** Get UFP VDM responder modal operation supported flag */
#define dpm_rx_ufp_vdm_ack_modal_opr_supported_get() \
    (g_dpm_info.rx_ufp_vdm_ack_modal_opr_supported)

/** Set UFP VDM responder modal operation supported flag  */
#define dpm_rx_ufp_vdm_ack_modal_opr_supported_set(val) \
    do { \
        g_dpm_info.rx_ufp_vdm_ack_modal_opr_supported=val; \
    } while(0)




/** Get received VDM ACK flag */
#define dpm_ufp_partner_prod_type_get() \
    (g_dpm_info.ufp_partner_prod_type)

/** Set received VDM ACK flag  */
#define dpm_ufp_partner_prod_type_set(val) \
    do { \
        g_dpm_info.ufp_partner_prod_type=val; \
    } while(0)


/** Get rx VDM ACK VID */
#define dpm_rx_ufp_vdm_ack_vid_get() \
    (g_dpm_info.rx_ufp_vdm_ack_vid)

/** Set rx VDM ACK VID */
#define dpm_rx_ufp_vdm_ack_vid_set(val) \
    do { \
        g_dpm_info.rx_ufp_vdm_ack_vid=val; \
    } while(0)


/** Get rx VDM ACK SVID */
#define dpm_rx_ufp_vdm_ack_svid_get() \
    (g_dpm_info.rx_ufp_vdm_ack_svid)

/** Set rx VDM ACK SVID */
#define dpm_rx_ufp_vdm_ack_svid_set(val) \
    do { \
        g_dpm_info.rx_ufp_vdm_ack_svid=val; \
    } while(0)


/** Get rx VDM ACK BCD device */
#define dpm_rx_ufp_vdm_ack_bcd_device_get() \
    (g_dpm_info.rx_ufp_vdm_ack_bcd_device)

/** Set rx VDM ACK BCD device */
#define dpm_rx_ufp_vdm_ack_bcd_device_set(val) \
    do { \
        g_dpm_info.rx_ufp_vdm_ack_bcd_device=val; \
    } while(0)


/** Get rx VDM ACK Product ID */
#define dpm_rx_ufp_vdm_ack_prod_id_get() \
    (g_dpm_info.rx_ufp_vdm_ack_prod_id)

/** Set rx VDM ACK Product ID */
#define dpm_rx_ufp_vdm_ack_prod_id_set(val) \
    do { \
        g_dpm_info.rx_ufp_vdm_ack_prod_id=val; \
    } while(0)


/** Get rx VDM ACK Test ID */
#define dpm_rx_ufp_vdm_ack_tid_get() \
    (g_dpm_info.rx_ufp_vdm_ack_tid)

/** Set rx VDM ACK Test ID */
#define dpm_rx_ufp_vdm_ack_tid_set(val) \
    do { \
        g_dpm_info.rx_ufp_vdm_ack_tid=val; \
    } while(0)



/** Get the sop' device product type */
#define dpm_partner_prod_type_get() \
    (g_dpm_info.partner_prod_type)

/** Set the sop' device product type  */
#define dpm_partner_prod_type_set(val) \
    do { \
        g_dpm_info.partner_prod_type=val; \
    } while(0)


/** Get the sop' device product type */
#define dpm_partner_prod_type_get() \
    (g_dpm_info.partner_prod_type)

/** Set the sop' device product type  */
#define dpm_partner_prod_type_set(val) \
    do { \
        g_dpm_info.partner_prod_type=val; \
    } while(0)


/** Require fast power role swap  */
#define dpm_frs_req_set(flg) \
    do { \
        g_dpm_info.frs_req = (flg); \
    } while(0)

/** Get fast power role swap require flag  */
#define dpm_frs_req_get() \
    (g_dpm_info.frs_req)


/** Set 5V source capability ibus to 2.4A flag */
#define dpm_source_cap_5v_change_ibus_2p4a_set(flg) \
    do { \
        g_dpm_info.source_cap_5v_change_ibus_2p4a = (flg); \
    } while(0)

/** Get 5V source capability ibus to 2.4A flag */
#define dpm_source_cap_5v_change_ibus_2p4a_get() \
    (g_dpm_info.source_cap_5v_change_ibus_2p4a)


/** Set source over current flag */
#define dpm_source_ocp_flag_set(flg) \
    do { \
        g_dpm_info.source_ocp_flag = (flg); \
    } while(0)

/** Get source over current flag */
#define dpm_source_ocp_flag_get() \
    (g_dpm_info.source_ocp_flag)


/** Set the flag that hard reset due to no current */
#define dpm_hrst_due_to_no_current_flag_set(flg) \
    do { \
        g_dpm_info.hrst_due_to_no_current_flag = (flg); \
    } while(0)

/** Get the flag that hard reset due to no current */
#define dpm_hrst_due_to_no_current_flag_get() \
    (g_dpm_info.hrst_due_to_no_current_flag)


/** Set port state, see DPM_PORT_STATE_t */
#define dpm_port_state_set(flg) \
    do { \
        g_dpm_info.port_state = (flg); \
    } while(0)
 /** Get port state, see DPM_PORT_STATE_t */
#define dpm_port_state_get() \
        (g_dpm_info.port_state)

/** Get epr mode enter fail cause, see DPM_PORT_STATE_t */
#define dpm_port_tx_epr_fail_cause_get() \
        (g_dpm_info.tx_epr_mode_data_enter_fail_cause)



    /** set epr mode enter fail cause, see DPM_PORT_STATE_t */
#define dpm_port_tx_epr_fail_cause_set(flg) \
        do { \
            g_dpm_info.tx_epr_mode_data_enter_fail_cause = (flg); \
        } while(0)
    
  
/** Set tx epr mode act, see DPM_PORT_STATE_t */
#define dpm_port_tx_epr_mode_act_set(flg) \
        do { \
            g_dpm_info.tx_epr_mode_msg_act = (flg); \
        } while(0)
/** Get tx epr mode act, see DPM_PORT_STATE_t */
#define dpm_port_tx_epr_mode_act_get() \
        (g_dpm_info.tx_epr_mode_msg_act)

/** Set port  epr mode state, see DPM_PORT_STATE_t */
#define dpm_port_epr_mode_set(flg) \
        do { \
            g_dpm_info.epr_mode = (flg); \
        } while(0)
/** Get port epr mode state , see DPM_PORT_STATE_t */
#define dpm_port_epr_mode_get() \
        (g_dpm_info.epr_mode)

/** Get port interrupt state: enabled(TRUE), disabled(FALSE) */
#define dpm_intr_state_get()        drv_pd_intr_en_get()

/** Set port interrupt state: enable(TRUE), disable(FALSE) */
#define dpm_intr_state_set(flg)     drv_pd_intr_en_set(flg)


/** Get VBUS discharge state: enabled(TRUE), disabled(FALSE) */
#define dpm_vbus_discharge_get() \
    (DRV_REG_FIELD_GET(DPM_REG_1,VBUS_DISCH))

/** Set VBUS discharge state: enable(TRUE), disable(FALSE) */
#define dpm_vbus_discharge_set(flg) \
    do { \
        DRV_REG_FIELD_SET(DPM_REG_1,VBUS_DISCH,(flg)); \
    } while(0)


extern volatile DPM_PORT_INFO_t g_dpm_info;


#if SYS_POWER_SRC_OCP_ENABLED
bool_t dpm_src_ocp_vbus_drop_check();
#endif /* SYS_POWER_SRC_OCP_ENABLED */

/** \brief DPM request new power level for test
 *
 * \return TRUE if execute successfully, else FALSE
 */
bool_t dpm_new_power_level_req();

u32_t dpm_vbus_volt_get();


/** \brief DPM VBUS voltage check
 *
 * \param volt input voltage to check if the current VBUS voltage is out of range
 * \return 1: in range, 0: out of range
 */
bool_t dpm_vbus_volt_check(u32_t volt);

/** \brief DPM snk VBUS voltage check
 *
 * \param volt input voltage to check if the current VBUS voltage is out of range
 * \return 1: in range, 0: out of range
 */
bool_t dpm_snk_vbus_volt_check(u32_t volt);


/** \brief DPM VBUS voltage drop check
 *
 * \return 1: dropped, 0: normal
 */
bool_t dpm_vbus_drop_check();

bool_t dpm_vbus_is_at_vsafe0v();

/** \brief DPM information reset
 *
 */
void dpm_info_reset();

/** \brief DPM otg mode check
 *
 */

void dpm_vbus_otg_mode_check();


bool_t dpm_epr_mode_evaluate_req();

bool_t dpm_epr_mode_evaluate_cable();


#endif /* #ifndef __DPM_PORT_H_ */


