/**
 * \file    reg_def_spi.h
 * \brief   Register definition file
 * 
 * \par     Copyright (c) 2019 UWE Technologies Corp., Ltd. All Rights Reserved.
 * \author  James
 * \date    2019-04-26
 * \version 
 * 
 * \history 
 *  Date        Note
 *  2019-04-26  Original Creation
 * 
 */

#ifndef __REG_DEF_SPI_H_
#define __REG_DEF_SPI_H_



#define SPSTA_REG                                       (0x40000A00)

/**
SPIF, RO, reset value(0x0)
Serial data transfer flag, set by hardware upon data transfer completion. Cleared by hardware when data transfer is in progress and
 Also could be cleared by reading SPSTA_REG.
*/
#ifndef SPIF
#define SPIF
#endif
#define SPSTA_REG_SPIF                                  (0x07)
#define SPSTA_REG_SPIF_WTH                              (0x01)
#define SPSTA_REG_SPIF_FLDSET                           (0x00000080)
#define SPSTA_REG_SPIF_FLDMSK                           (0xFFFFFF7F)

/**
WCOL, RO, reset value(0x0)
Write collision Flag, set by hardware upon write collision to "SPDAT_REG". Cleared by hardware upon data 
Transfer completion when no collision has occurred. Can also be cleared by an access to "SPSTA_REG" 
And an access to "SPSTA_REG".
*/
#ifndef WCOL
#define WCOL
#endif
#define SPSTA_REG_WCOL                                  (0x06)
#define SPSTA_REG_WCOL_WTH                              (0x01)
#define SPSTA_REG_WCOL_FLDSET                           (0x00000040)
#define SPSTA_REG_WCOL_FLDMSK                           (0xFFFFFFBF)

/**
SSER, RO, reset value(0x0)
Synchronous Serial Slave Error flag. 
Set by hardware when "ssn" input is deasserted before the end of receive sequence.
Cleared by disabling the SPI module (clearing "spen" bit in "SPCON_REG".
*/
#ifndef SSER
#define SSER
#endif
#define SPSTA_REG_SSER                                  (0x05)
#define SPSTA_REG_SSER_WTH                              (0x01)
#define SPSTA_REG_SSER_FLDSET                           (0x00000020)
#define SPSTA_REG_SSER_FLDMSK                           (0xFFFFFFDF)

/**
MODF, RO, reset value(0x0)
Mode fault flag.
Set by hardware when the "ssn" pin level is in conflict with actual mode of SPI controller (configured as
Master while externally selected as slave). Cleared by hardware when "ssn" pin is at appropriate level or 
Cleared by software by reading the SPSTA_REG.
*/
#ifndef MODF
#define MODF
#endif
#define SPSTA_REG_MODF                                  (0x04)
#define SPSTA_REG_MODF_WTH                              (0x01)
#define SPSTA_REG_MODF_FLDSET                           (0x00000010)
#define SPSTA_REG_MODF_FLDMSK                           (0xFFFFFFEF)


#define SPCON_REG                                       (0x40000A04)

/**
SPEN, RW, reset value(0x0)
SPI interface enable bus "spen[3:0]" 
*/
#ifndef SPEN
#define SPEN
#endif
#define SPCON_REG_SPEN                                  (0x08)
#define SPCON_REG_SPEN_WTH                              (0x04)
#define SPCON_REG_SPEN_FLDSET                           (0x00000F00)
#define SPCON_REG_SPEN_FLDMSK                           (0xFFFFF0FF)

/**
SPFRM, RW, reset value(0x0)
1'b1 : 16 bit SPI frame mode; 1'b0 : 8 bit SPI frame mode.
*/
#ifndef SPFRM
#define SPFRM
#endif
#define SPCON_REG_SPFRM                                 (0x07)
#define SPCON_REG_SPFRM_WTH                             (0x01)
#define SPCON_REG_SPFRM_FLDSET                          (0x00000080)
#define SPCON_REG_SPFRM_FLDMSK                          (0xFFFFFF7F)

/**
SPR2, RW, reset value(0x0)
together with SPR1, SPR0 defines the clock rate in master mode
*/
#ifndef SPR2
#define SPR2
#endif
#define SPCON_REG_SPR2                                  (0x06)
#define SPCON_REG_SPR2_WTH                              (0x01)
#define SPCON_REG_SPR2_FLDSET                           (0x00000040)
#define SPCON_REG_SPR2_FLDMSK                           (0xFFFFFFBF)

/**
SSDIS, RW, reset value(0x0)
when cleared enables the "ssn" input in both master and slave modes. When set disables the "ssn" input 
In both master and slave modes. 
In slave mode, this bit has no effect if "cpha=0". When "ssdis" is set, no "modf" interrupt request is generated.
*/
#ifndef SSDIS
#define SSDIS
#endif
#define SPCON_REG_SSDIS                                 (0x05)
#define SPCON_REG_SSDIS_WTH                             (0x01)
#define SPCON_REG_SSDIS_FLDSET                          (0x00000020)
#define SPCON_REG_SSDIS_FLDMSK                          (0xFFFFFFDF)

/**
MSTR, RW, reset value(0x1)
1'b0 : SPI slave mode; 1'b1 : SPI master mode
*/
#ifndef MSTR
#define MSTR
#endif
#define SPCON_REG_MSTR                                  (0x04)
#define SPCON_REG_MSTR_WTH                              (0x01)
#define SPCON_REG_MSTR_FLDSET                           (0x00000010)
#define SPCON_REG_MSTR_FLDMSK                           (0xFFFFFFEF)

/**
CPOL, RW, reset value(0x0)
clock polarity, when cleared the "sck" is set to 0 in idle state.
When set the "sck" is set to 1 in idle state.
*/
#ifndef CPOL
#define CPOL
#endif
#define SPCON_REG_CPOL                                  (0x03)
#define SPCON_REG_CPOL_WTH                              (0x01)
#define SPCON_REG_CPOL_FLDSET                           (0x00000008)
#define SPCON_REG_CPOL_FLDMSK                           (0xFFFFFFF7)

/**
CPHA, RW, reset value(0x1)
clock phase: 
when cleared, data is sampled when the "sck" leaves the idle state (see CPOL).
When set, data is sampled when the "sck" returns to idle state (see CPOL).
*/
#ifndef CPHA
#define CPHA
#endif
#define SPCON_REG_CPHA                                  (0x02)
#define SPCON_REG_CPHA_WTH                              (0x01)
#define SPCON_REG_CPHA_FLDSET                           (0x00000004)
#define SPCON_REG_CPHA_FLDMSK                           (0xFFFFFFFB)

/**
SPR1, RW, reset value(0x0)
SPR2,SPR1,SPR0 together defines the sck rate in master mode :
3'b000 : Fclk/2
3'b001 : Fclk/4
3'b010 : Fclk/8
3'b011 : Fclk/16
3'b100 : Fclk/32
3'b101 : Fclk/64
3'b110 : Fclk/128
3'b111 : the master clock is not generated.

*/
#ifndef SPR1
#define SPR1
#endif
#define SPCON_REG_SPR1                                  (0x01)
#define SPCON_REG_SPR1_WTH                              (0x01)
#define SPCON_REG_SPR1_FLDSET                           (0x00000002)
#define SPCON_REG_SPR1_FLDMSK                           (0xFFFFFFFD)

/**
SPR0, RW, reset value(0x0)

*/
#ifndef SPR0
#define SPR0
#endif
#define SPCON_REG_SPR0                                  (0x00)
#define SPCON_REG_SPR0_WTH                              (0x01)
#define SPCON_REG_SPR0_FLDSET                           (0x00000001)
#define SPCON_REG_SPR0_FLDMSK                           (0xFFFFFFFE)


#define SPDAT_REG                                       (0x40000A08)

/**
SPDAT, RW, reset value(0x0)
when writing to the SPDAT, TX data is placed directly into the shift register.
When reading the SPDAT returns the RX data value located in the receive buffer, not the shift register.
*/
#ifndef SPDAT
#define SPDAT
#endif
#define SPDAT_REG_SPDAT                                 (0x00)
#define SPDAT_REG_SPDAT_WTH                             (0x10)
#define SPDAT_REG_SPDAT_FLDSET                          (0x0000FFFF)
#define SPDAT_REG_SPDAT_FLDMSK                          (0xFFFF0000)


#define SPSSN_REG                                       (0x40000A0C)

/**
SPSSN, RW, reset value(0xFF)
the SPSSN is a read/write register used to control the "spssn[3:0]" output bus of SPI.
*/
#ifndef SPSSN
#define SPSSN
#endif
#define SPSSN_REG_SPSSN                                 (0x00)
#define SPSSN_REG_SPSSN_WTH                             (0x04)
#define SPSSN_REG_SPSSN_FLDSET                          (0x0000000F)
#define SPSSN_REG_SPSSN_FLDMSK                          (0xFFFFFFF0)


#define SPINT_REG                                       (0x40000A10)

/**
INTSPI, RO, reset value(0x0)
Two status flags can generate interrupt request of SPI:
1: "spif" when transmission is finished, this flag is set by hardware.
2: "modf" this bit is set when the level on "ssn" input is in conflict with actual mode. i.e. it is '0' in
      Master mode (if "ssdis" = '0').
The interrupt request is cleared when both flags "spif" and "modf" are cleared.
*/
#ifndef INTSPI
#define INTSPI
#endif
#define SPINT_REG_INTSPI                                (0x00)
#define SPINT_REG_INTSPI_WTH                            (0x01)
#define SPINT_REG_INTSPI_FLDSET                         (0x00000001)
#define SPINT_REG_INTSPI_FLDMSK                         (0xFFFFFFFE)



#endif /* #ifndef __REG_DEF_SPI_H_ */

