/**
 * \file    reg_def_i2c.h
 * \brief   Register definition file
 * 
 * \par     Copyright (c) 2019 UWE Technologies Corp., Ltd. All Rights Reserved.
 * \author  James
 * \date    2019-04-26
 * \version 
 * 
 * \history 
 *  Date        Note
 *  2019-04-26  Original Creation
 * 
 */

#ifndef __REG_DEF_I2C_H_
#define __REG_DEF_I2C_H_



#define I2C_DATA_REG                                    (0x40000700)

/**
I2C_DAT, RW, reset value(0x0)
I2C received or transmit data register
*/
#ifndef I2C_DAT
#define I2C_DAT
#endif
#define I2C_DATA_REG_I2C_DAT                            (0x00)
#define I2C_DATA_REG_I2C_DAT_WTH                        (0x08)
#define I2C_DATA_REG_I2C_DAT_FLDSET                     (0x000000FF)
#define I2C_DATA_REG_I2C_DAT_FLDMSK                     (0xFFFFFF00)


#define I2C_ADR_REG                                     (0x40000704)

/**
SLV_ADDR, RW, reset value(0x0)
I2C slave address
*/
#ifndef SLV_ADDR
#define SLV_ADDR
#endif
#define I2C_ADR_REG_SLV_ADDR                            (0x01)
#define I2C_ADR_REG_SLV_ADDR_WTH                        (0x07)
#define I2C_ADR_REG_SLV_ADDR_FLDSET                     (0x000000FE)
#define I2C_ADR_REG_SLV_ADDR_FLDMSK                     (0xFFFFFF01)

/**
GC, RW, reset value(0x0)
if set this bit, the general call address is recognized, otherwise it is ignored.
*/
#ifndef GC
#define GC
#endif
#define I2C_ADR_REG_GC                                  (0x00)
#define I2C_ADR_REG_GC_WTH                              (0x01)
#define I2C_ADR_REG_GC_FLDSET                           (0x00000001)
#define I2C_ADR_REG_GC_FLDMSK                           (0xFFFFFFFE)


#define I2C_CTRL_REG                                    (0x40000708)

/**
I2C_ENA, RW, reset value(0x0)
I2C enable bit
*/
#ifndef I2C_ENA
#define I2C_ENA
#endif
#define I2C_CTRL_REG_I2C_ENA                            (0x06)
#define I2C_CTRL_REG_I2C_ENA_WTH                        (0x01)
#define I2C_CTRL_REG_I2C_ENA_FLDSET                     (0x00000040)
#define I2C_CTRL_REG_I2C_ENA_FLDMSK                     (0xFFFFFFBF)

/**
STA, RW, reset value(0x0)
Start flag, when sta=1, I2C check the bus status, if free, the start signal will be generated.
*/
#ifndef STA
#define STA
#endif
#define I2C_CTRL_REG_STA                                (0x05)
#define I2C_CTRL_REG_STA_WTH                            (0x01)
#define I2C_CTRL_REG_STA_FLDSET                         (0x00000020)
#define I2C_CTRL_REG_STA_FLDMSK                         (0xFFFFFFDF)

/**
STO, RW, reset value(0x0)
Stop flag, when sto=1 and I2C is maste mode, the stop signal will be generated.
*/
#ifndef STO
#define STO
#endif
#define I2C_CTRL_REG_STO                                (0x04)
#define I2C_CTRL_REG_STO_WTH                            (0x01)
#define I2C_CTRL_REG_STO_FLDSET                         (0x00000010)
#define I2C_CTRL_REG_STO_FLDMSK                         (0xFFFFFFEF)

/**
SI, RW, reset value(0x0)
Serial interrupt flag, set by HW, clear by SW write 0 to this bit.
*/
#ifndef SI
#define SI
#endif
#define I2C_CTRL_REG_SI                                 (0x03)
#define I2C_CTRL_REG_SI_WTH                             (0x01)
#define I2C_CTRL_REG_SI_FLDSET                          (0x00000008)
#define I2C_CTRL_REG_SI_FLDMSK                          (0xFFFFFFF7)

/**
AA, RW, reset value(0x0)
when SW set aa=1, an "acknowledge" will be returned, otherwise an "NAK" will be returned.
*/
#ifndef AA
#define AA
#endif
#define I2C_CTRL_REG_AA                                 (0x02)
#define I2C_CTRL_REG_AA_WTH                             (0x01)
#define I2C_CTRL_REG_AA_FLDSET                          (0x00000004)
#define I2C_CTRL_REG_AA_FLDMSK                          (0xFFFFFFFB)


#define I2C_FREQ_REG                                    (0x4000070C)

/**
CNT2_DIV, RW, reset value(0x0)
Counter 2 divider
*/
#ifndef CNT2_DIV
#define CNT2_DIV
#endif
#define I2C_FREQ_REG_CNT2_DIV                           (0x04)
#define I2C_FREQ_REG_CNT2_DIV_WTH                       (0x04)
#define I2C_FREQ_REG_CNT2_DIV_FLDSET                    (0x000000F0)
#define I2C_FREQ_REG_CNT2_DIV_FLDMSK                    (0xFFFFFF0F)

/**
CNT1_DIV, RW, reset value(0x0)
Counter 1 divider
*/
#ifndef CNT1_DIV
#define CNT1_DIV
#endif
#define I2C_FREQ_REG_CNT1_DIV                           (0x00)
#define I2C_FREQ_REG_CNT1_DIV_WTH                       (0x04)
#define I2C_FREQ_REG_CNT1_DIV_FLDSET                    (0x0000000F)
#define I2C_FREQ_REG_CNT1_DIV_FLDMSK                    (0xFFFFFFF0)


#define I2C_STA_REG                                     (0x40000710)

/**
STATUS, RO, reset value(0x1f)
I2C status code.
*/
#ifndef STATUS
#define STATUS
#endif
#define I2C_STA_REG_STATUS                              (0x03)
#define I2C_STA_REG_STATUS_WTH                          (0x05)
#define I2C_STA_REG_STATUS_FLDSET                       (0x000000F8)
#define I2C_STA_REG_STATUS_FLDMSK                       (0xFFFFFF07)


#define I2C_SMB_SEL_REG                                 (0x40000714)

/**
SMB_EN, RW, reset value(0x0)
SMBUS extension enable
*/
#ifndef SMB_EN
#define SMB_EN
#endif
#define I2C_SMB_SEL_REG_SMB_EN                          (0x07)
#define I2C_SMB_SEL_REG_SMB_EN_WTH                      (0x01)
#define I2C_SMB_SEL_REG_SMB_EN_FLDSET                   (0x00000080)
#define I2C_SMB_SEL_REG_SMB_EN_FLDMSK                   (0xFFFFFF7F)

/**
SMB_SEL, RW, reset value(0x0)
select one of the timeout register for read/write access through the SMB_DST register
*/
#ifndef SMB_SEL
#define SMB_SEL
#endif
#define I2C_SMB_SEL_REG_SMB_SEL                         (0x00)
#define I2C_SMB_SEL_REG_SMB_SEL_WTH                     (0x03)
#define I2C_SMB_SEL_REG_SMB_SEL_FLDSET                  (0x00000007)
#define I2C_SMB_SEL_REG_SMB_SEL_FLDMSK                  (0xFFFFFFF8)


#define I2C_SMB_DST_REG                                 (0x40000718)

/**
SMB_DST, RW, reset value(0x35)
The optional System Management Bus (SMBus) protocol hardware implementation features:
- timeout detection (clock low timeout measurement)
- Tmext timeout detection (cumulative stretch clock cycles within one byte)
- Tsext timeout detection (cumulative stretch clock cycles between start and stop condition)
The SMBus requires two additional registers: smb_sel and smb_dst. They both form a read/write access port to the timeout registers.
*/
#ifndef SMB_DST
#define SMB_DST
#endif
#define I2C_SMB_DST_REG_SMB_DST                         (0x00)
#define I2C_SMB_DST_REG_SMB_DST_WTH                     (0x08)
#define I2C_SMB_DST_REG_SMB_DST_FLDSET                  (0x000000FF)
#define I2C_SMB_DST_REG_SMB_DST_FLDMSK                  (0xFFFFFF00)


#define SEC_I2C_DATA_REG                                (0x40000800)

/**
I2C_DAT, RW, reset value(0x0)
I2C received or transmit data register
*/
#ifndef I2C_DAT
#define I2C_DAT
#endif
#define SEC_I2C_DATA_REG_I2C_DAT                        (0x00)
#define SEC_I2C_DATA_REG_I2C_DAT_WTH                    (0x08)
#define SEC_I2C_DATA_REG_I2C_DAT_FLDSET                 (0x000000FF)
#define SEC_I2C_DATA_REG_I2C_DAT_FLDMSK                 (0xFFFFFF00)


#define SEC_I2C_ADR_REG                                 (0x40000804)

/**
SLV_ADDR, RW, reset value(0x0)
I2C slave address
*/
#ifndef SLV_ADDR
#define SLV_ADDR
#endif
#define SEC_I2C_ADR_REG_SLV_ADDR                        (0x01)
#define SEC_I2C_ADR_REG_SLV_ADDR_WTH                    (0x07)
#define SEC_I2C_ADR_REG_SLV_ADDR_FLDSET                 (0x000000FE)
#define SEC_I2C_ADR_REG_SLV_ADDR_FLDMSK                 (0xFFFFFF01)

/**
GC, RW, reset value(0x0)
if set this bit, the general call address is recognized, otherwise it is ignored.
*/
#ifndef GC
#define GC
#endif
#define SEC_I2C_ADR_REG_GC                              (0x00)
#define SEC_I2C_ADR_REG_GC_WTH                          (0x01)
#define SEC_I2C_ADR_REG_GC_FLDSET                       (0x00000001)
#define SEC_I2C_ADR_REG_GC_FLDMSK                       (0xFFFFFFFE)


#define SEC_I2C_CTRL_REG                                (0x40000808)

/**
I2C_ENA, RW, reset value(0x0)
I2C enable bit
*/
#ifndef I2C_ENA
#define I2C_ENA
#endif
#define SEC_I2C_CTRL_REG_I2C_ENA                        (0x06)
#define SEC_I2C_CTRL_REG_I2C_ENA_WTH                    (0x01)
#define SEC_I2C_CTRL_REG_I2C_ENA_FLDSET                 (0x00000040)
#define SEC_I2C_CTRL_REG_I2C_ENA_FLDMSK                 (0xFFFFFFBF)

/**
STA, RW, reset value(0x0)
Start flag, when sta=1, I2C check the bus status, if free, the start signal will be generated.
*/
#ifndef STA
#define STA
#endif
#define SEC_I2C_CTRL_REG_STA                            (0x05)
#define SEC_I2C_CTRL_REG_STA_WTH                        (0x01)
#define SEC_I2C_CTRL_REG_STA_FLDSET                     (0x00000020)
#define SEC_I2C_CTRL_REG_STA_FLDMSK                     (0xFFFFFFDF)

/**
STO, RW, reset value(0x0)
Stop flag, when sto=1 and I2C is maste mode, the stop signal will be generated.
*/
#ifndef STO
#define STO
#endif
#define SEC_I2C_CTRL_REG_STO                            (0x04)
#define SEC_I2C_CTRL_REG_STO_WTH                        (0x01)
#define SEC_I2C_CTRL_REG_STO_FLDSET                     (0x00000010)
#define SEC_I2C_CTRL_REG_STO_FLDMSK                     (0xFFFFFFEF)

/**
SI, RW, reset value(0x0)
Serial interrupt flag, set by HW, clear by SW write 0 to this bit.
*/
#ifndef SI
#define SI
#endif
#define SEC_I2C_CTRL_REG_SI                             (0x03)
#define SEC_I2C_CTRL_REG_SI_WTH                         (0x01)
#define SEC_I2C_CTRL_REG_SI_FLDSET                      (0x00000008)
#define SEC_I2C_CTRL_REG_SI_FLDMSK                      (0xFFFFFFF7)

/**
AA, RW, reset value(0x0)
when SW set aa=1, an "acknowledge" will be returned, otherwise an "NAK" will be returned.
*/
#ifndef AA
#define AA
#endif
#define SEC_I2C_CTRL_REG_AA                             (0x02)
#define SEC_I2C_CTRL_REG_AA_WTH                         (0x01)
#define SEC_I2C_CTRL_REG_AA_FLDSET                      (0x00000004)
#define SEC_I2C_CTRL_REG_AA_FLDMSK                      (0xFFFFFFFB)


#define SEC_I2C_FREQ_REG                                (0x4000080C)

/**
CNT2_DIV, RW, reset value(0x0)
Counter 2 divider, the valid smallest value is 1.
*/
#ifndef CNT2_DIV
#define CNT2_DIV
#endif
#define SEC_I2C_FREQ_REG_CNT2_DIV                       (0x04)
#define SEC_I2C_FREQ_REG_CNT2_DIV_WTH                   (0x04)
#define SEC_I2C_FREQ_REG_CNT2_DIV_FLDSET                (0x000000F0)
#define SEC_I2C_FREQ_REG_CNT2_DIV_FLDMSK                (0xFFFFFF0F)

/**
CNT1_DIV, RW, reset value(0x0)
Counter 1 divider, the valid smallest value is 1.
I2C SCL frequency = SYS_CLK_Freq/(4*(CONT2_DIV+1)*(CNT1_DIV+1))
*/
#ifndef CNT1_DIV
#define CNT1_DIV
#endif
#define SEC_I2C_FREQ_REG_CNT1_DIV                       (0x00)
#define SEC_I2C_FREQ_REG_CNT1_DIV_WTH                   (0x04)
#define SEC_I2C_FREQ_REG_CNT1_DIV_FLDSET                (0x0000000F)
#define SEC_I2C_FREQ_REG_CNT1_DIV_FLDMSK                (0xFFFFFFF0)


#define SEC_I2C_STA_REG                                 (0x40000810)

/**
STATUS, RO, reset value(0x1f)
I2C status code.
*/
#ifndef STATUS
#define STATUS
#endif
#define SEC_I2C_STA_REG_STATUS                          (0x03)
#define SEC_I2C_STA_REG_STATUS_WTH                      (0x05)
#define SEC_I2C_STA_REG_STATUS_FLDSET                   (0x000000F8)
#define SEC_I2C_STA_REG_STATUS_FLDMSK                   (0xFFFFFF07)


#define SEC_I2C_SMB_SEL_REG                             (0x40000814)

/**
SMB_EN, RW, reset value(0x0)
SMBUS extension enable
*/
#ifndef SMB_EN
#define SMB_EN
#endif
#define SEC_I2C_SMB_SEL_REG_SMB_EN                      (0x07)
#define SEC_I2C_SMB_SEL_REG_SMB_EN_WTH                  (0x01)
#define SEC_I2C_SMB_SEL_REG_SMB_EN_FLDSET               (0x00000080)
#define SEC_I2C_SMB_SEL_REG_SMB_EN_FLDMSK               (0xFFFFFF7F)

/**
SMB_SEL, RW, reset value(0x0)
select one of the timeout register for read/write access through the SMB_DST register
*/
#ifndef SMB_SEL
#define SMB_SEL
#endif
#define SEC_I2C_SMB_SEL_REG_SMB_SEL                     (0x00)
#define SEC_I2C_SMB_SEL_REG_SMB_SEL_WTH                 (0x03)
#define SEC_I2C_SMB_SEL_REG_SMB_SEL_FLDSET              (0x00000007)
#define SEC_I2C_SMB_SEL_REG_SMB_SEL_FLDMSK              (0xFFFFFFF8)


#define SEC_I2C_SMB_DST_REG                             (0x40000818)

/**
SMB_DST, RW, reset value(0x35)
The optional System Management Bus (SMBus) protocol hardware implementation features:
- timeout detection (clock low timeout measurement)
- Tmext timeout detection (cumulative stretch clock cycles within one byte)
- Tsext timeout detection (cumulative stretch clock cycles between start and stop condition)
The SMBus requires two additional registers: smb_sel and smb_dst. They both form a read/write access port to the timeout registers.
*/
#ifndef SMB_DST
#define SMB_DST
#endif
#define SEC_I2C_SMB_DST_REG_SMB_DST                     (0x00)
#define SEC_I2C_SMB_DST_REG_SMB_DST_WTH                 (0x08)
#define SEC_I2C_SMB_DST_REG_SMB_DST_FLDSET              (0x000000FF)
#define SEC_I2C_SMB_DST_REG_SMB_DST_FLDMSK              (0xFFFFFF00)



#endif /* #ifndef __REG_DEF_I2C_H_ */

