/**
 * \file    reg_def_gpio.h
 * \brief   Register definition file
 * 
 * \par     Copyright (c) 2019 UWE Technologies Corp., Ltd. All Rights Reserved.
 * \author  James
 * \date    2019-04-26
 * \version 
 * 
 * \history 
 *  Date        Note
 *  2019-04-26  Original Creation
 * 
 */

#ifndef __REG_DEF_GPIO_H_
#define __REG_DEF_GPIO_H_



#define GPIO_EN_REG                                     (0x40000048)

/**
GPIO_EN, RW, reset value(0xFF87FE7F)
GPIO  enable, 1: GPIO mode is selected, 0: function mode is selected, pin work as UART or I2C and so on.
*/
#ifndef GPIO_EN
#define GPIO_EN
#endif
#define GPIO_EN_REG_GPIO_EN                             (0x00)
#define GPIO_EN_REG_GPIO_EN_WTH                         (0x20)
#define GPIO_EN_REG_GPIO_EN_FLDSET                      (0xFFFFFFFF)
#define GPIO_EN_REG_GPIO_EN_FLDMSK                      (0x00000000)


#define GPIO_DR_REG                                     (0x40000B00)

/**
P0_DR, RW, reset value(0x0)
Port 0 output data register, SW could write this register to decide GPIO's output values
*/
#ifndef P0_DR
#define P0_DR
#endif
#define GPIO_DR_REG_P0_DR                               (0x00)
#define GPIO_DR_REG_P0_DR_WTH                           (0x20)
#define GPIO_DR_REG_P0_DR_FLDSET                        (0xFFFFFFFF)
#define GPIO_DR_REG_P0_DR_FLDMSK                        (0x00000000)


#define GPIO_DDR_REG                                    (0x40000B04)

/**
P0_DDR, RW, reset value(0x0)
Port 0 direction register, 0 : input; 1 : output.
*/
#ifndef P0_DDR
#define P0_DDR
#endif
#define GPIO_DDR_REG_P0_DDR                             (0x00)
#define GPIO_DDR_REG_P0_DDR_WTH                         (0x20)
#define GPIO_DDR_REG_P0_DDR_FLDSET                      (0xFFFFFFFF)
#define GPIO_DDR_REG_P0_DDR_FLDMSK                      (0x00000000)


#define GPIO_DSR_REG                                    (0x40000B08)

/**
P0_DSR, RO, reset value(0x0)
Port 0 data source register, these register's value is fixed as 0, which indicate all P0's data value is decide by SW 
*/
#ifndef P0_DSR
#define P0_DSR
#endif
#define GPIO_DSR_REG_P0_DSR                             (0x00)
#define GPIO_DSR_REG_P0_DSR_WTH                         (0x20)
#define GPIO_DSR_REG_P0_DSR_FLDSET                      (0xFFFFFFFF)
#define GPIO_DSR_REG_P0_DSR_FLDMSK                      (0x00000000)


#define GPIO_INT_EN_REG                                 (0x40000B0C)

/**
P0_INT_EN, RW, reset value(0x0)
Port 0 interrupts enable bits
*/
#ifndef P0_INT_EN
#define P0_INT_EN
#endif
#define GPIO_INT_EN_REG_P0_INT_EN                       (0x00)
#define GPIO_INT_EN_REG_P0_INT_EN_WTH                   (0x20)
#define GPIO_INT_EN_REG_P0_INT_EN_FLDSET                (0xFFFFFFFF)
#define GPIO_INT_EN_REG_P0_INT_EN_FLDMSK                (0x00000000)


#define GPIO_INT_MASK_REG                               (0x40000B10)

/**
P0_INT_MASK, RW, reset value(0x0)
Port 0 interrupts mask bits
*/
#ifndef P0_INT_MASK
#define P0_INT_MASK
#endif
#define GPIO_INT_MASK_REG_P0_INT_MASK                   (0x00)
#define GPIO_INT_MASK_REG_P0_INT_MASK_WTH               (0x20)
#define GPIO_INT_MASK_REG_P0_INT_MASK_FLDSET            (0xFFFFFFFF)
#define GPIO_INT_MASK_REG_P0_INT_MASK_FLDMSK            (0x00000000)


#define GPIO_INT_TYPE_REG                               (0x40000B14)

/**
P0_INT_TYPE, RW, reset value(0x0)
Port 0 interrupts trigger type control bits, 0 : level trigger interrupt; 1 : edge trigger interrupt
*/
#ifndef P0_INT_TYPE
#define P0_INT_TYPE
#endif
#define GPIO_INT_TYPE_REG_P0_INT_TYPE                   (0x00)
#define GPIO_INT_TYPE_REG_P0_INT_TYPE_WTH               (0x20)
#define GPIO_INT_TYPE_REG_P0_INT_TYPE_FLDSET            (0xFFFFFFFF)
#define GPIO_INT_TYPE_REG_P0_INT_TYPE_FLDMSK            (0x00000000)


#define GPIO_INT_POLAR_REG                              (0x40000B18)

/**
P0_INT_POLAR, RW, reset value(0x0)
Port 0 interrupts trigger polarity control bits, 0 : low level or falling edge trigger interrupt; 1 : high level or rising edge trigger interrupt
*/
#ifndef P0_INT_POLAR
#define P0_INT_POLAR
#endif
#define GPIO_INT_POLAR_REG_P0_INT_POLAR                 (0x00)
#define GPIO_INT_POLAR_REG_P0_INT_POLAR_WTH             (0x20)
#define GPIO_INT_POLAR_REG_P0_INT_POLAR_FLDSET          (0xFFFFFFFF)
#define GPIO_INT_POLAR_REG_P0_INT_POLAR_FLDMSK          (0x00000000)


#define GPIO_INT_STATUS_REG                             (0x40000B1C)

/**
P0_INT_STATUS, RO, reset value(0x0)
Port 0 masked interrupt status registers
*/
#ifndef P0_INT_STATUS
#define P0_INT_STATUS
#endif
#define GPIO_INT_STATUS_REG_P0_INT_STATUS               (0x00)
#define GPIO_INT_STATUS_REG_P0_INT_STATUS_WTH           (0x20)
#define GPIO_INT_STATUS_REG_P0_INT_STATUS_FLDSET        (0xFFFFFFFF)
#define GPIO_INT_STATUS_REG_P0_INT_STATUS_FLDMSK        (0x00000000)


#define GPIO_RAW_INT_STATUS_REG                         (0x40000B20)

/**
P0_RAW_INT_STATUS, RO, reset value(0x0)
Port 0 raw interrupt status registers
*/
#ifndef P0_RAW_INT_STATUS
#define P0_RAW_INT_STATUS
#endif
#define GPIO_RAW_INT_STATUS_REG_P0_RAW_INT_STATUS       (0x00)
#define GPIO_RAW_INT_STATUS_REG_P0_RAW_INT_STATUS_WTH   (0x20)
#define GPIO_RAW_INT_STATUS_REG_P0_RAW_INT_STATUS_FLDSET (0xFFFFFFFF)
#define GPIO_RAW_INT_STATUS_REG_P0_RAW_INT_STATUS_FLDMSK (0x00000000)


#define GPIO_INT_CLR_REG                                (0x40000B24)

/**
P0_INT_CLR, WO, reset value(0x0)
Port 0  interrupt write clear registers, SW write this register bits to clear corresponding interrupt status bit. Write only, could not read
*/
#ifndef P0_INT_CLR
#define P0_INT_CLR
#endif
#define GPIO_INT_CLR_REG_P0_INT_CLR                     (0x00)
#define GPIO_INT_CLR_REG_P0_INT_CLR_WTH                 (0x20)
#define GPIO_INT_CLR_REG_P0_INT_CLR_FLDSET              (0xFFFFFFFF)
#define GPIO_INT_CLR_REG_P0_INT_CLR_FLDMSK              (0x00000000)


#define GPIO_IDR_REG                                    (0x40000B28)

/**
P0_IDR, RO, reset value(0x0)
Port 0 input data register, SW could read this register to know GPIO's input values
*/
#ifndef P0_IDR
#define P0_IDR
#endif
#define GPIO_IDR_REG_P0_IDR                             (0x00)
#define GPIO_IDR_REG_P0_IDR_WTH                         (0x20)
#define GPIO_IDR_REG_P0_IDR_FLDSET                      (0xFFFFFFFF)
#define GPIO_IDR_REG_P0_IDR_FLDMSK                      (0x00000000)


#define GPIO_INT_SYNC_REG                               (0x40000B2C)

/**
P0_INT_SYNC, RW, reset value(0x0)
Registers to control Port 0 interrupts generate sync with clock or not.
*/
#ifndef P0_INT_SYNC
#define P0_INT_SYNC
#endif
#define GPIO_INT_SYNC_REG_P0_INT_SYNC                   (0x00)
#define GPIO_INT_SYNC_REG_P0_INT_SYNC_WTH               (0x20)
#define GPIO_INT_SYNC_REG_P0_INT_SYNC_FLDSET            (0xFFFFFFFF)
#define GPIO_INT_SYNC_REG_P0_INT_SYNC_FLDMSK            (0x00000000)


#define GPIO_BIT_MASK_REG                               (0x40000B30)

/**
P0_BIT_MASK, RW, reset value(0x0)
when GPIO direction is output, configure the mask bit could mask the write for P0_DR register by bit.
*/
#ifndef P0_BIT_MASK
#define P0_BIT_MASK
#endif
#define GPIO_BIT_MASK_REG_P0_BIT_MASK                   (0x00)
#define GPIO_BIT_MASK_REG_P0_BIT_MASK_WTH               (0x20)
#define GPIO_BIT_MASK_REG_P0_BIT_MASK_FLDSET            (0xFFFFFFFF)
#define GPIO_BIT_MASK_REG_P0_BIT_MASK_FLDMSK            (0x00000000)


#define GPIO_PD_REG                                     (0x40000B34)

/**
PD, RW, reset value(0x7)
GPIO Pull-Dn resistor Enable
*/
#ifndef PD
#define PD
#endif
#define GPIO_PD_REG_PD                                  (0x00)
#define GPIO_PD_REG_PD_WTH                              (0x20)
#define GPIO_PD_REG_PD_FLDSET                           (0xFFFFFFFF)
#define GPIO_PD_REG_PD_FLDMSK                           (0x00000000)


#define GPIO_PU_REG                                     (0x40000B38)

/**
PU, RW, reset value(0x0)
GPIO Pull-Up resistor Enable
*/
#ifndef PU
#define PU
#endif
#define GPIO_PU_REG_PU                                  (0x00)
#define GPIO_PU_REG_PU_WTH                              (0x20)
#define GPIO_PU_REG_PU_FLDSET                           (0xFFFFFFFF)
#define GPIO_PU_REG_PU_FLDMSK                           (0x00000000)


#define GPIO_ODRV0_REG                                  (0x40000B3C)

/**
ODRV0, RW, reset value(0x0)
GPIO PAD output driver control:
2'b00 : Normal mode;
2'b01 : NMOS open-drain w/o internal pull-up;
2'b10 : NMOS open-drain with 10 KOhm pull-up;
2'b11 : NMOS open-drain with 1 Kohm pull-up.
*/
#ifndef ODRV0
#define ODRV0
#endif
#define GPIO_ODRV0_REG_ODRV0                            (0x00)
#define GPIO_ODRV0_REG_ODRV0_WTH                        (0x20)
#define GPIO_ODRV0_REG_ODRV0_FLDSET                     (0xFFFFFFFF)
#define GPIO_ODRV0_REG_ODRV0_FLDMSK                     (0x00000000)


#define GPIO_ODRV1_REG                                  (0x40000B40)

/**
ODRV1, RW, reset value(0x0)

*/
#ifndef ODRV1
#define ODRV1
#endif
#define GPIO_ODRV1_REG_ODRV1                            (0x00)
#define GPIO_ODRV1_REG_ODRV1_WTH                        (0x20)
#define GPIO_ODRV1_REG_ODRV1_FLDSET                     (0xFFFFFFFF)
#define GPIO_ODRV1_REG_ODRV1_FLDMSK                     (0x00000000)


#define GPIO_SEN_REG                                    (0x40000B44)

/**
SEN, RW, reset value(0x0)
GPIO PAD input schmiter buffer enable
*/
#ifndef SEN
#define SEN
#endif
#define GPIO_SEN_REG_SEN                                (0x00)
#define GPIO_SEN_REG_SEN_WTH                            (0x20)
#define GPIO_SEN_REG_SEN_FLDSET                         (0xFFFFFFFF)
#define GPIO_SEN_REG_SEN_FLDMSK                         (0x00000000)


#define GPIO_ES0_REG                                    (0x40000B48)

/**
ES0, RW, reset value(0x0)
GPIO PAD output driver control:
2'b00 : 4 mA;
2'b01 : 6 mA;
2'b10 : 8 mA;
2'b11 : 10 mA.
*/
#ifndef ES0
#define ES0
#endif
#define GPIO_ES0_REG_ES0                                (0x00)
#define GPIO_ES0_REG_ES0_WTH                            (0x20)
#define GPIO_ES0_REG_ES0_FLDSET                         (0xFFFFFFFF)
#define GPIO_ES0_REG_ES0_FLDMSK                         (0x00000000)


#define GPIO_ES1_REG                                    (0x40000B4C)

/**
ES1, RW, reset value(0x0)

*/
#ifndef ES1
#define ES1
#endif
#define GPIO_ES1_REG_ES1                                (0x00)
#define GPIO_ES1_REG_ES1_WTH                            (0x20)
#define GPIO_ES1_REG_ES1_FLDSET                         (0xFFFFFFFF)
#define GPIO_ES1_REG_ES1_FLDMSK                         (0x00000000)



#endif /* #ifndef __REG_DEF_GPIO_H_ */

