/**
 * \file    reg_def_dma.h
 * \brief   Register definition file
 * 
 * \par     Copyright (c) 2019 UWE Technologies Corp., Ltd. All Rights Reserved.
 * \author  James
 * \date    2019-04-26
 * \version 
 * 
 * \history 
 *  Date        Note
 *  2019-04-26  Original Creation
 * 
 */

#ifndef __REG_DEF_DMA_H_
#define __REG_DEF_DMA_H_



#define DMA0_CTRL_REG0                                  (0x40000070)

/**
DMA_SRC_START_ADDR, RW, reset value(0x0)
DMA source data start address
*/
#ifndef DMA_SRC_START_ADDR
#define DMA_SRC_START_ADDR
#endif
#define DMA0_CTRL_REG0_DMA_SRC_START_ADDR               (0x00)
#define DMA0_CTRL_REG0_DMA_SRC_START_ADDR_WTH           (0x20)
#define DMA0_CTRL_REG0_DMA_SRC_START_ADDR_FLDSET        (0xFFFFFFFF)
#define DMA0_CTRL_REG0_DMA_SRC_START_ADDR_FLDMSK        (0x00000000)


#define DMA0_CTRL_REG1                                  (0x40000074)

/**
DMA_DES_START_ADDR, RW, reset value(0x0)
DMA destination data start address
*/
#ifndef DMA_DES_START_ADDR
#define DMA_DES_START_ADDR
#endif
#define DMA0_CTRL_REG1_DMA_DES_START_ADDR               (0x00)
#define DMA0_CTRL_REG1_DMA_DES_START_ADDR_WTH           (0x20)
#define DMA0_CTRL_REG1_DMA_DES_START_ADDR_FLDSET        (0xFFFFFFFF)
#define DMA0_CTRL_REG1_DMA_DES_START_ADDR_FLDMSK        (0x00000000)


#define DMA0_CTRL_REG2                                  (0x40000078)

/**
DMA_BUSY, RW, reset value(0x0)
1: start DMA data move operation, set by SW and cleared by HW
*/
#ifndef DMA_BUSY
#define DMA_BUSY
#endif
#define DMA0_CTRL_REG2_DMA_BUSY                         (0x1F)
#define DMA0_CTRL_REG2_DMA_BUSY_WTH                     (0x01)
#define DMA0_CTRL_REG2_DMA_BUSY_FLDSET                  (0x80000000)
#define DMA0_CTRL_REG2_DMA_BUSY_FLDMSK                  (0x7FFFFFFF)

/**
DMA_MODE, RW, reset value(0x0)
2'b00: address increment mode. 
2'b01: address decent mode
2'b10: source address hold constant mode.
2'b11: destination address hold constant mode.
*/
#ifndef DMA_MODE
#define DMA_MODE
#endif
#define DMA0_CTRL_REG2_DMA_MODE                         (0x1D)
#define DMA0_CTRL_REG2_DMA_MODE_WTH                     (0x02)
#define DMA0_CTRL_REG2_DMA_MODE_FLDSET                  (0x60000000)
#define DMA0_CTRL_REG2_DMA_MODE_FLDMSK                  (0x9FFFFFFF)

/**
DMA_BYTE_CNT, RW, reset value(0x0)
DMA data length, in unit of bytes 
*/
#ifndef DMA_BYTE_CNT
#define DMA_BYTE_CNT
#endif
#define DMA0_CTRL_REG2_DMA_BYTE_CNT                     (0x00)
#define DMA0_CTRL_REG2_DMA_BYTE_CNT_WTH                 (0x18)
#define DMA0_CTRL_REG2_DMA_BYTE_CNT_FLDSET              (0x00FFFFFF)
#define DMA0_CTRL_REG2_DMA_BYTE_CNT_FLDMSK              (0xFF000000)


#define DMA1_CTRL_REG0                                  (0x40000080)

/**
DMA_SRC_START_ADDR, RW, reset value(0x0)
DMA source data start address
*/
#ifndef DMA_SRC_START_ADDR
#define DMA_SRC_START_ADDR
#endif
#define DMA1_CTRL_REG0_DMA_SRC_START_ADDR               (0x00)
#define DMA1_CTRL_REG0_DMA_SRC_START_ADDR_WTH           (0x20)
#define DMA1_CTRL_REG0_DMA_SRC_START_ADDR_FLDSET        (0xFFFFFFFF)
#define DMA1_CTRL_REG0_DMA_SRC_START_ADDR_FLDMSK        (0x00000000)


#define DMA1_CTRL_REG1                                  (0x40000084)

/**
DMA_DES_START_ADDR, RW, reset value(0x0)
DMA destination data start address
*/
#ifndef DMA_DES_START_ADDR
#define DMA_DES_START_ADDR
#endif
#define DMA1_CTRL_REG1_DMA_DES_START_ADDR               (0x00)
#define DMA1_CTRL_REG1_DMA_DES_START_ADDR_WTH           (0x20)
#define DMA1_CTRL_REG1_DMA_DES_START_ADDR_FLDSET        (0xFFFFFFFF)
#define DMA1_CTRL_REG1_DMA_DES_START_ADDR_FLDMSK        (0x00000000)


#define DMA1_CTRL_REG2                                  (0x40000088)

/**
DMA_BUSY, RW, reset value(0x0)
1: start DMA data move operation, set by SW and cleared by HW
*/
#ifndef DMA_BUSY
#define DMA_BUSY
#endif
#define DMA1_CTRL_REG2_DMA_BUSY                         (0x1F)
#define DMA1_CTRL_REG2_DMA_BUSY_WTH                     (0x01)
#define DMA1_CTRL_REG2_DMA_BUSY_FLDSET                  (0x80000000)
#define DMA1_CTRL_REG2_DMA_BUSY_FLDMSK                  (0x7FFFFFFF)

/**
DMA_MODE, RW, reset value(0x0)
2'b00: address increment mode. 
2'b01: address decent mode
2'b10: source address hold constant mode.
2'b11: destination address hold constant mode.
*/
#ifndef DMA_MODE
#define DMA_MODE
#endif
#define DMA1_CTRL_REG2_DMA_MODE                         (0x1D)
#define DMA1_CTRL_REG2_DMA_MODE_WTH                     (0x02)
#define DMA1_CTRL_REG2_DMA_MODE_FLDSET                  (0x60000000)
#define DMA1_CTRL_REG2_DMA_MODE_FLDMSK                  (0x9FFFFFFF)

/**
DMA_BYTE_CNT, RW, reset value(0x0)
DMA data length, in unit of bytes 
*/
#ifndef DMA_BYTE_CNT
#define DMA_BYTE_CNT
#endif
#define DMA1_CTRL_REG2_DMA_BYTE_CNT                     (0x00)
#define DMA1_CTRL_REG2_DMA_BYTE_CNT_WTH                 (0x18)
#define DMA1_CTRL_REG2_DMA_BYTE_CNT_FLDSET              (0x00FFFFFF)
#define DMA1_CTRL_REG2_DMA_BYTE_CNT_FLDMSK              (0xFF000000)


#define DMA_INT_REG                                     (0x4000008C)

/**
DMA1_INT_ENA, RW, reset value(0x0)
DMA interrupt enable.
*/
#ifndef DMA1_INT_ENA
#define DMA1_INT_ENA
#endif
#define DMA_INT_REG_DMA1_INT_ENA                        (0x03)
#define DMA_INT_REG_DMA1_INT_ENA_WTH                    (0x01)
#define DMA_INT_REG_DMA1_INT_ENA_FLDSET                 (0x00000008)
#define DMA_INT_REG_DMA1_INT_ENA_FLDMSK                 (0xFFFFFFF7)

/**
DMA1_INT_STATUS, RC, reset value(0x0)
DMA interrupt status
*/
#ifndef DMA1_INT_STATUS
#define DMA1_INT_STATUS
#endif
#define DMA_INT_REG_DMA1_INT_STATUS                     (0x02)
#define DMA_INT_REG_DMA1_INT_STATUS_WTH                 (0x01)
#define DMA_INT_REG_DMA1_INT_STATUS_FLDSET              (0x00000004)
#define DMA_INT_REG_DMA1_INT_STATUS_FLDMSK              (0xFFFFFFFB)

/**
DMA0_INT_ENA, RW, reset value(0x0)
DMA interrupt enable.
*/
#ifndef DMA0_INT_ENA
#define DMA0_INT_ENA
#endif
#define DMA_INT_REG_DMA0_INT_ENA                        (0x01)
#define DMA_INT_REG_DMA0_INT_ENA_WTH                    (0x01)
#define DMA_INT_REG_DMA0_INT_ENA_FLDSET                 (0x00000002)
#define DMA_INT_REG_DMA0_INT_ENA_FLDMSK                 (0xFFFFFFFD)

/**
DMA0_INT_STATUS, RC, reset value(0x0)
DMA interrupt status
*/
#ifndef DMA0_INT_STATUS
#define DMA0_INT_STATUS
#endif
#define DMA_INT_REG_DMA0_INT_STATUS                     (0x00)
#define DMA_INT_REG_DMA0_INT_STATUS_WTH                 (0x01)
#define DMA_INT_REG_DMA0_INT_STATUS_FLDSET              (0x00000001)
#define DMA_INT_REG_DMA0_INT_STATUS_FLDMSK              (0xFFFFFFFE)



#endif /* #ifndef __REG_DEF_DMA_H_ */

