/**
 * \file    reg_def_chip.h
 * \brief   Register definition file
 * 
 * \par     Copyright (c) 2019 UWE Technologies Corp., Ltd. All Rights Reserved.
 * \author  James
 * \date    2019-04-26
 * \version 
 * 
 * \history 
 *  Date        Note
 *  2019-04-26  Original Creation
 * 
 */

#ifndef __REG_DEF_CHIP_H_
#define __REG_DEF_CHIP_H_



#define CHIP_REG_0                                      (0x40000000)

/**
CHIP_RST, WC, reset value(0x0)
Chip reset
*/
#ifndef CHIP_RST
#define CHIP_RST
#endif
#define CHIP_REG_0_CHIP_RST                             (0x07)
#define CHIP_REG_0_CHIP_RST_WTH                         (0x01)
#define CHIP_REG_0_CHIP_RST_FLDSET                      (0x00000080)
#define CHIP_REG_0_CHIP_RST_FLDMSK                      (0xFFFFFF7F)

/**
VERSION_ID, RO, reset value(0x2)
Version ID xxx
*/
#ifndef VERSION_ID
#define VERSION_ID
#endif
#define CHIP_REG_0_VERSION_ID                           (0x00)
#define CHIP_REG_0_VERSION_ID_WTH                       (0x06)
#define CHIP_REG_0_VERSION_ID_FLDSET                    (0x0000003F)
#define CHIP_REG_0_VERSION_ID_FLDMSK                    (0xFFFFFFC0)


#define PRG_ADDR_OFFSET_REG                             (0x40000030)

/**
PRG_ADDR_OFFSET, RW, reset value(0x0)
Program page address offset
*/
#ifndef PRG_ADDR_OFFSET
#define PRG_ADDR_OFFSET
#endif
#define PRG_ADDR_OFFSET_REG_PRG_ADDR_OFFSET             (0x0C)
#define PRG_ADDR_OFFSET_REG_PRG_ADDR_OFFSET_WTH         (0x14)
#define PRG_ADDR_OFFSET_REG_PRG_ADDR_OFFSET_FLDSET      (0xFFFFF000)
#define PRG_ADDR_OFFSET_REG_PRG_ADDR_OFFSET_FLDMSK      (0x00000FFF)


#define MCU_INT_INDEX_REG                               (0x40000090)

/**
INT7_INDEX, RW, reset value(0x7)
MCU interrupt vector mapping index.
3'h0 : pd_int is connected to MCU core corresponding int_vector bit;
3'h1 : dma_int is connected to MCU core corresponding int_vector bit;
3'h2 : i2c_int is  connected to MCU core corresponding int_vector bit;
3'h3 : sec_i2c_int is  connected to MCU core corresponding int_vector bit;
3'h4 : uart0_int is connected to MCU core corresponding int_vector bit;
3'h5 :  uart1_int is connected to MCU core corresponding int_vector bit;
3'h6 : spi_int is connected to MCU core corresponding int_vector bit;
3'h7 :  gpio_int is connected to MCU core corresponding int_vector bit;
*/
#ifndef INT7_INDEX
#define INT7_INDEX
#endif
#define MCU_INT_INDEX_REG_INT7_INDEX                    (0x1C)
#define MCU_INT_INDEX_REG_INT7_INDEX_WTH                (0x03)
#define MCU_INT_INDEX_REG_INT7_INDEX_FLDSET             (0x70000000)
#define MCU_INT_INDEX_REG_INT7_INDEX_FLDMSK             (0x8FFFFFFF)

/**
INT6_INDEX, RW, reset value(0x6 )
*/
#ifndef INT6_INDEX
#define INT6_INDEX
#endif
#define MCU_INT_INDEX_REG_INT6_INDEX                    (0x18)
#define MCU_INT_INDEX_REG_INT6_INDEX_WTH                (0x03)
#define MCU_INT_INDEX_REG_INT6_INDEX_FLDSET             (0x07000000)
#define MCU_INT_INDEX_REG_INT6_INDEX_FLDMSK             (0xF8FFFFFF)

/**
INT5_INDEX, RW, reset value(0x5)
*/
#ifndef INT5_INDEX
#define INT5_INDEX
#endif
#define MCU_INT_INDEX_REG_INT5_INDEX                    (0x14)
#define MCU_INT_INDEX_REG_INT5_INDEX_WTH                (0x03)
#define MCU_INT_INDEX_REG_INT5_INDEX_FLDSET             (0x00700000)
#define MCU_INT_INDEX_REG_INT5_INDEX_FLDMSK             (0xFF8FFFFF)

/**
INT4_INDEX, RW, reset value(0x4)
*/
#ifndef INT4_INDEX
#define INT4_INDEX
#endif
#define MCU_INT_INDEX_REG_INT4_INDEX                    (0x10)
#define MCU_INT_INDEX_REG_INT4_INDEX_WTH                (0x03)
#define MCU_INT_INDEX_REG_INT4_INDEX_FLDSET             (0x00070000)
#define MCU_INT_INDEX_REG_INT4_INDEX_FLDMSK             (0xFFF8FFFF)

/**
INT3_INDEX, RW, reset value(0x3)
*/
#ifndef INT3_INDEX
#define INT3_INDEX
#endif
#define MCU_INT_INDEX_REG_INT3_INDEX                    (0x0C)
#define MCU_INT_INDEX_REG_INT3_INDEX_WTH                (0x03)
#define MCU_INT_INDEX_REG_INT3_INDEX_FLDSET             (0x00007000)
#define MCU_INT_INDEX_REG_INT3_INDEX_FLDMSK             (0xFFFF8FFF)

/**
INT2_INDEX, RW, reset value(0x2)
*/
#ifndef INT2_INDEX
#define INT2_INDEX
#endif
#define MCU_INT_INDEX_REG_INT2_INDEX                    (0x08)
#define MCU_INT_INDEX_REG_INT2_INDEX_WTH                (0x03)
#define MCU_INT_INDEX_REG_INT2_INDEX_FLDSET             (0x00000700)
#define MCU_INT_INDEX_REG_INT2_INDEX_FLDMSK             (0xFFFFF8FF)

/**
INT1_INDEX, RW, reset value(0x1)
*/
#ifndef INT1_INDEX
#define INT1_INDEX
#endif
#define MCU_INT_INDEX_REG_INT1_INDEX                    (0x04)
#define MCU_INT_INDEX_REG_INT1_INDEX_WTH                (0x03)
#define MCU_INT_INDEX_REG_INT1_INDEX_FLDSET             (0x00000070)
#define MCU_INT_INDEX_REG_INT1_INDEX_FLDMSK             (0xFFFFFF8F)

/**
INT0_INDEX, RW, reset value(0x0)
*/
#ifndef INT0_INDEX
#define INT0_INDEX
#endif
#define MCU_INT_INDEX_REG_INT0_INDEX                    (0x00)
#define MCU_INT_INDEX_REG_INT0_INDEX_WTH                (0x03)
#define MCU_INT_INDEX_REG_INT0_INDEX_FLDSET             (0x00000007)
#define MCU_INT_INDEX_REG_INT0_INDEX_FLDMSK             (0xFFFFFFF8)


#define DPM_LPM_REG                                     (0x40000094)

/**
T_RES, RW, reset value(0x14E)
 Twup, for GSMC FLASH, 10 us
*/
#ifndef T_RES
#define T_RES
#endif
#define DPM_LPM_REG_T_RES                               (0x10)
#define DPM_LPM_REG_T_RES_WTH                           (0x09)
#define DPM_LPM_REG_T_RES_FLDSET                        (0x01FF0000)
#define DPM_LPM_REG_T_RES_FLDMSK                        (0xFE00FFFF)

/**
SLP_MODE, RW, reset value(0x0)
1'b1: chip enter sleep mode
*/
#ifndef SLP_MODE
#define SLP_MODE
#endif
#define DPM_LPM_REG_SLP_MODE                            (0x08)
#define DPM_LPM_REG_SLP_MODE_WTH                        (0x01)
#define DPM_LPM_REG_SLP_MODE_FLDSET                     (0x00000100)
#define DPM_LPM_REG_SLP_MODE_FLDMSK                     (0xFFFFFEFF)

/**
SLP_AUTO_WAKEUP_TIMER, RW, reset value(0x0)
HW sleep auto wake up timer
*/
#ifndef SLP_AUTO_WAKEUP_TIMER
#define SLP_AUTO_WAKEUP_TIMER
#endif
#define DPM_LPM_REG_SLP_AUTO_WAKEUP_TIMER               (0x00)
#define DPM_LPM_REG_SLP_AUTO_WAKEUP_TIMER_WTH           (0x08)
#define DPM_LPM_REG_SLP_AUTO_WAKEUP_TIMER_FLDSET        (0x000000FF)
#define DPM_LPM_REG_SLP_AUTO_WAKEUP_TIMER_FLDMSK        (0xFFFFFF00)


#define CRC_CTRL_REG                                    (0x400000A0)

/**
CRC_BIT_ORDER, RW, reset value(0x0)
1'b0: input data MSB first, 1'b1: input data LSB first.
*/
#ifndef CRC_BIT_ORDER
#define CRC_BIT_ORDER
#endif
#define CRC_CTRL_REG_CRC_BIT_ORDER                      (0x03)
#define CRC_CTRL_REG_CRC_BIT_ORDER_WTH                  (0x01)
#define CRC_CTRL_REG_CRC_BIT_ORDER_FLDSET               (0x00000008)
#define CRC_CTRL_REG_CRC_BIT_ORDER_FLDMSK               (0xFFFFFFF7)

/**
CRC_CALC_MODE, RW, reset value(0x0)
2'b00: Reserved; 
2'b01: CRC8, x^8 + x^5 + x^4 + x^3 + 1
2'b10: CRC16, x^16 + x^15 + x^2 + 1
2'b11: CRC32, x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x^1 + 1
*/
#ifndef CRC_CALC_MODE
#define CRC_CALC_MODE
#endif
#define CRC_CTRL_REG_CRC_CALC_MODE                      (0x00)
#define CRC_CTRL_REG_CRC_CALC_MODE_WTH                  (0x02)
#define CRC_CTRL_REG_CRC_CALC_MODE_FLDSET               (0x00000003)
#define CRC_CTRL_REG_CRC_CALC_MODE_FLDMSK               (0xFFFFFFFC)


#define CRC_INIT_REG                                    (0x400000A4)

/**
CRC_INIT_VALUE, RW, reset value(0x0)
CRC calculate register initial value
*/
#ifndef CRC_INIT_VALUE
#define CRC_INIT_VALUE
#endif
#define CRC_INIT_REG_CRC_INIT_VALUE                     (0x00)
#define CRC_INIT_REG_CRC_INIT_VALUE_WTH                 (0x20)
#define CRC_INIT_REG_CRC_INIT_VALUE_FLDSET              (0xFFFFFFFF)
#define CRC_INIT_REG_CRC_INIT_VALUE_FLDMSK              (0x00000000)


#define CRC_DATA_REG                                    (0x400000A8)

/**
CRC_DATA, RW, reset value(0x0)
Input DATA, fixed 8 bit width
*/
#ifndef CRC_DATA
#define CRC_DATA
#endif
#define CRC_DATA_REG_CRC_DATA                           (0x00)
#define CRC_DATA_REG_CRC_DATA_WTH                       (0x08)
#define CRC_DATA_REG_CRC_DATA_FLDSET                    (0x000000FF)
#define CRC_DATA_REG_CRC_DATA_FLDMSK                    (0xFFFFFF00)


#define CRC_RSLT_REG                                    (0x400000AC)

/**
CRC_RSLT_VALUE, RO, reset value(0x0)
CRC calculate result register
*/
#ifndef CRC_RSLT_VALUE
#define CRC_RSLT_VALUE
#endif
#define CRC_RSLT_REG_CRC_RSLT_VALUE                     (0x00)
#define CRC_RSLT_REG_CRC_RSLT_VALUE_WTH                 (0x20)
#define CRC_RSLT_REG_CRC_RSLT_VALUE_FLDSET              (0xFFFFFFFF)
#define CRC_RSLT_REG_CRC_RSLT_VALUE_FLDMSK              (0x00000000)


#define PLL_CFG_REG                                     (0x400000C0)

/**
PLL_CLK_SEL, RW, reset value(0X0)
1'b0: 4 MHz ROSC clock is selected as system clock, 1'b1 : PLL output clock is selected. SW should configure this bit to high, when PLL_LOCKED is high.
*/
#ifndef PLL_CLK_SEL
#define PLL_CLK_SEL
#endif
#define PLL_CFG_REG_PLL_CLK_SEL                         (0x09)
#define PLL_CFG_REG_PLL_CLK_SEL_WTH                     (0x01)
#define PLL_CFG_REG_PLL_CLK_SEL_FLDSET                  (0x00000200)
#define PLL_CFG_REG_PLL_CLK_SEL_FLDMSK                  (0xFFFFFDFF)

/**
PLL_LOCKED, RO, reset value(0X0)
PLL LOCK indication.
*/
#ifndef PLL_LOCKED
#define PLL_LOCKED
#endif
#define PLL_CFG_REG_PLL_LOCKED                          (0x08)
#define PLL_CFG_REG_PLL_LOCKED_WTH                      (0x01)
#define PLL_CFG_REG_PLL_LOCKED_FLDSET                   (0x00000100)
#define PLL_CFG_REG_PLL_LOCKED_FLDMSK                   (0xFFFFFEFF)

/**
DN, RW, reset value(0X4)
Frequency of output clock: Fout = Fref*DN/DP, 
DP[1:0] is encode as below
2'b00 : DP=1,
2'b01 : DP=2,
2'b10 : DP=4,
2'b11 : DP=8.
*/
#ifndef DN
#define DN
#endif
#define PLL_CFG_REG_DN                                  (0x02)
#define PLL_CFG_REG_DN_WTH                              (0x06)
#define PLL_CFG_REG_DN_FLDSET                           (0x000000FC)
#define PLL_CFG_REG_DN_FLDMSK                           (0xFFFFFF03)

/**
DP, RW, reset value(0X0)
*/
#ifndef DP
#define DP
#endif
#define PLL_CFG_REG_DP                                  (0x00)
#define PLL_CFG_REG_DP_WTH                              (0x02)
#define PLL_CFG_REG_DP_FLDSET                           (0x00000003)
#define PLL_CFG_REG_DP_FLDMSK                           (0xFFFFFFFC)


#define ROSC_CFG_REG                                    (0x400000C4)

/**
TUNE, RW, reset value(0x0)
ROSC frequency tune control registers
*/
#ifndef TUNE
#define TUNE
#endif
#define ROSC_CFG_REG_TUNE                               (0x01)
#define ROSC_CFG_REG_TUNE_WTH                           (0x05)
#define ROSC_CFG_REG_TUNE_FLDSET                        (0x0000003E)
#define ROSC_CFG_REG_TUNE_FLDMSK                        (0xFFFFFFC1)

/**
TSEL, RW, reset value(0x1)
ROSC frequency tune select register, 1'b1 : tuned by TRIM fuse. 1'b0: tuned by internal tune registers
*/
#ifndef TSEL
#define TSEL
#endif
#define ROSC_CFG_REG_TSEL                               (0x00)
#define ROSC_CFG_REG_TSEL_WTH                           (0x01)
#define ROSC_CFG_REG_TSEL_FLDSET                        (0x00000001)
#define ROSC_CFG_REG_TSEL_FLDMSK                        (0xFFFFFFFE)


#define ANA_TRIM_REG                                    (0x400000C8)

/**
TURNBG, RW, reset value(0x0)
LDO2, LDO3 Band-Gap trimming control:
*/
#ifndef TURNBG
#define TURNBG
#endif
#define ANA_TRIM_REG_TURNBG                             (0x13)
#define ANA_TRIM_REG_TURNBG_WTH                         (0x05)
#define ANA_TRIM_REG_TURNBG_FLDSET                      (0x00F80000)
#define ANA_TRIM_REG_TURNBG_FLDMSK                      (0xFF07FFFF)

/**
TUNE33, RW, reset value(0x0)
LDO1 Band-Gap trimming control:
*/
#ifndef TUNE33
#define TUNE33
#endif
#define ANA_TRIM_REG_TUNE33                             (0x0E)
#define ANA_TRIM_REG_TUNE33_WTH                         (0x05)
#define ANA_TRIM_REG_TUNE33_FLDSET                      (0x0007C000)
#define ANA_TRIM_REG_TUNE33_FLDMSK                      (0xFFF83FFF)

/**
ITRIM, RW, reset value(0x0)
current source trim reg
*/
#ifndef ITRIM
#define ITRIM
#endif
#define ANA_TRIM_REG_ITRIM                              (0x08)
#define ANA_TRIM_REG_ITRIM_WTH                          (0x06)
#define ANA_TRIM_REG_ITRIM_FLDSET                       (0x00003F00)
#define ANA_TRIM_REG_ITRIM_FLDMSK                       (0xFFFFC0FF)

/**
RDTRIM2, RW, reset value(0x0)
Rd2 trim reg
*/
#ifndef RDTRIM2
#define RDTRIM2
#endif
#define ANA_TRIM_REG_RDTRIM2                            (0x04)
#define ANA_TRIM_REG_RDTRIM2_WTH                        (0x04)
#define ANA_TRIM_REG_RDTRIM2_FLDSET                     (0x000000F0)
#define ANA_TRIM_REG_RDTRIM2_FLDMSK                     (0xFFFFFF0F)

/**
RDTRIM1, RW, reset value(0x0)
Rd1 trim reg
*/
#ifndef RDTRIM1
#define RDTRIM1
#endif
#define ANA_TRIM_REG_RDTRIM1                            (0x00)
#define ANA_TRIM_REG_RDTRIM1_WTH                        (0x04)
#define ANA_TRIM_REG_RDTRIM1_FLDSET                     (0x0000000F)
#define ANA_TRIM_REG_RDTRIM1_FLDMSK                     (0xFFFFFFF0)


#define SW_CTRL_REG                                     (0x400000CC)

/**
DP1SW500, RW, reset value(0x0)
1: enable 500 Kohm pull-down resister on DP1
*/
#ifndef DP1SW500
#define DP1SW500
#endif
#define SW_CTRL_REG_DP1SW500                            (0x07)
#define SW_CTRL_REG_DP1SW500_WTH                        (0x01)
#define SW_CTRL_REG_DP1SW500_FLDSET                     (0x00000080)
#define SW_CTRL_REG_DP1SW500_FLDMSK                     (0xFFFFFF7F)

/**
DP1SW20, RW, reset value(0x0)
1: enable 20 Kohm pull-down resister on DP1
*/
#ifndef DP1SW20
#define DP1SW20
#endif
#define SW_CTRL_REG_DP1SW20                             (0x06)
#define SW_CTRL_REG_DP1SW20_WTH                         (0x01)
#define SW_CTRL_REG_DP1SW20_FLDSET                      (0x00000040)
#define SW_CTRL_REG_DP1SW20_FLDMSK                      (0xFFFFFFBF)

/**
DM1SW20, RW, reset value(0x0)
1: enable 20 Kohm pull-down resister on DM1
*/
#ifndef DM1SW20
#define DM1SW20
#endif
#define SW_CTRL_REG_DM1SW20                             (0x05)
#define SW_CTRL_REG_DM1SW20_WTH                         (0x01)
#define SW_CTRL_REG_DM1SW20_FLDSET                      (0x00000020)
#define SW_CTRL_REG_DM1SW20_FLDMSK                      (0xFFFFFFDF)

/**
DP0SW500, RW, reset value(0x0)
1: enable 500 Kohm pull-down resister on DP0
*/
#ifndef DP0SW500
#define DP0SW500
#endif
#define SW_CTRL_REG_DP0SW500                            (0x04)
#define SW_CTRL_REG_DP0SW500_WTH                        (0x01)
#define SW_CTRL_REG_DP0SW500_FLDSET                     (0x00000010)
#define SW_CTRL_REG_DP0SW500_FLDMSK                     (0xFFFFFFEF)

/**
DP0SW20, RW, reset value(0x0)
1: enable 20 Kohm pull-down resister on DP0
*/
#ifndef DP0SW20
#define DP0SW20
#endif
#define SW_CTRL_REG_DP0SW20                             (0x03)
#define SW_CTRL_REG_DP0SW20_WTH                         (0x01)
#define SW_CTRL_REG_DP0SW20_FLDSET                      (0x00000008)
#define SW_CTRL_REG_DP0SW20_FLDMSK                      (0xFFFFFFF7)

/**
DM0SW20, RW, reset value(0x0)
1: enable 20 Kohm pull-down resister on DM0
*/
#ifndef DM0SW20
#define DM0SW20
#endif
#define SW_CTRL_REG_DM0SW20                             (0x02)
#define SW_CTRL_REG_DM0SW20_WTH                         (0x01)
#define SW_CTRL_REG_DM0SW20_FLDSET                      (0x00000004)
#define SW_CTRL_REG_DM0SW20_FLDMSK                      (0xFFFFFFFB)

/**
SW1R20, RW, reset value(0x0)
short DP0 and DM0
*/
#ifndef SW1R20
#define SW1R20
#endif
#define SW_CTRL_REG_SW1R20                              (0x01)
#define SW_CTRL_REG_SW1R20_WTH                          (0x01)
#define SW_CTRL_REG_SW1R20_FLDSET                       (0x00000002)
#define SW_CTRL_REG_SW1R20_FLDMSK                       (0xFFFFFFFD)

/**
SW0R20, RW, reset value(0x0)
short DP1 and DM1
*/
#ifndef SW0R20
#define SW0R20
#endif
#define SW_CTRL_REG_SW0R20                              (0x00)
#define SW_CTRL_REG_SW0R20_WTH                          (0x01)
#define SW_CTRL_REG_SW0R20_FLDSET                       (0x00000001)
#define SW_CTRL_REG_SW0R20_FLDMSK                       (0xFFFFFFFE)


#define PD_CTRL_REG                                     (0x400000D0)

/**
IGAIN, RW, reset value(0x0)
Current sense PGA Gain control.  1'b0 : 15 times, 1'b1 : 31 times.
*/
#ifndef IGAIN
#define IGAIN
#endif
#define PD_CTRL_REG_IGAIN                               (0x06)
#define PD_CTRL_REG_IGAIN_WTH                           (0x01)
#define PD_CTRL_REG_IGAIN_FLDSET                        (0x00000040)
#define PD_CTRL_REG_IGAIN_FLDMSK                        (0xFFFFFFBF)

/**
PDISEN, RW, reset value(0x1)
Power-down current sense control
*/
#ifndef PDISEN
#define PDISEN
#endif
#define PD_CTRL_REG_PDISEN                              (0x05)
#define PD_CTRL_REG_PDISEN_WTH                          (0x01)
#define PD_CTRL_REG_PDISEN_FLDSET                       (0x00000020)
#define PD_CTRL_REG_PDISEN_FLDMSK                       (0xFFFFFFDF)

/**
PDREF, RW, reset value(0x1)
Power-down reference control
*/
#ifndef PDREF
#define PDREF
#endif
#define PD_CTRL_REG_PDREF                               (0x04)
#define PD_CTRL_REG_PDREF_WTH                           (0x01)
#define PD_CTRL_REG_PDREF_FLDSET                        (0x00000010)
#define PD_CTRL_REG_PDREF_FLDMSK                        (0xFFFFFFEF)

/**
PDCC, RW, reset value(0x1)
Power-down CC wakeup
*/
#ifndef PDCC
#define PDCC
#endif
#define PD_CTRL_REG_PDCC                                (0x03)
#define PD_CTRL_REG_PDCC_WTH                            (0x01)
#define PD_CTRL_REG_PDCC_FLDSET                         (0x00000008)
#define PD_CTRL_REG_PDCC_FLDMSK                         (0xFFFFFFF7)

/**
PD431, RW, reset value(0x0)
Power-down 431 AMP control
*/
#ifndef PD431
#define PD431
#endif
#define PD_CTRL_REG_PD431                               (0x02)
#define PD_CTRL_REG_PD431_WTH                           (0x01)
#define PD_CTRL_REG_PD431_FLDSET                        (0x00000004)
#define PD_CTRL_REG_PD431_FLDMSK                        (0xFFFFFFFB)

/**
PD10U, RW, reset value(0x1)
AMP431 loading control. 1'b0 : 10 uA loading, 1'b1 : No loading.
*/
#ifndef PD10U
#define PD10U
#endif
#define PD_CTRL_REG_PD10U                               (0x01)
#define PD_CTRL_REG_PD10U_WTH                           (0x01)
#define PD_CTRL_REG_PD10U_FLDSET                        (0x00000002)
#define PD_CTRL_REG_PD10U_FLDMSK                        (0xFFFFFFFD)

/**
PDSAR, RW, reset value(0x1)
Power-down SAR ADC, 1'b1 : Power-down, 1'b0 : Power-on
*/
#ifndef PDSAR
#define PDSAR
#endif
#define PD_CTRL_REG_PDSAR                               (0x00)
#define PD_CTRL_REG_PDSAR_WTH                           (0x01)
#define PD_CTRL_REG_PDSAR_FLDSET                        (0x00000001)
#define PD_CTRL_REG_PDSAR_FLDMSK                        (0xFFFFFFFE)


#define DA_CTRL_REG                                     (0x400000D4)

/**
PDDA2, RW, reset value(0x1)
Power-down DAC, 1: power down, 0: power on
*/
#ifndef PDDA2
#define PDDA2
#endif
#define DA_CTRL_REG_PDDA2                               (0x1F)
#define DA_CTRL_REG_PDDA2_WTH                           (0x01)
#define DA_CTRL_REG_PDDA2_FLDSET                        (0x80000000)
#define DA_CTRL_REG_PDDA2_FLDMSK                        (0x7FFFFFFF)

/**
DAIN2, RW, reset value(0x0)
DA input
*/
#ifndef DAIN2
#define DAIN2
#endif
#define DA_CTRL_REG_DAIN2                               (0x10)
#define DA_CTRL_REG_DAIN2_WTH                           (0x0A)
#define DA_CTRL_REG_DAIN2_FLDSET                        (0x03FF0000)
#define DA_CTRL_REG_DAIN2_FLDMSK                        (0xFC00FFFF)

/**
PDDA3, RW, reset value(0x1)
Power-down DAC, 1: power down, 0: power on
*/
#ifndef PDDA3
#define PDDA3
#endif
#define DA_CTRL_REG_PDDA3                               (0x0F)
#define DA_CTRL_REG_PDDA3_WTH                           (0x01)
#define DA_CTRL_REG_PDDA3_FLDSET                        (0x00008000)
#define DA_CTRL_REG_PDDA3_FLDMSK                        (0xFFFF7FFF)

/**
DAIN3, RW, reset value(0x0)
DA input
*/
#ifndef DAIN3
#define DAIN3
#endif
#define DA_CTRL_REG_DAIN3                               (0x00)
#define DA_CTRL_REG_DAIN3_WTH                           (0x07)
#define DA_CTRL_REG_DAIN3_FLDSET                        (0x0000007F)
#define DA_CTRL_REG_DAIN3_FLDMSK                        (0xFFFFFF80)



#endif /* #ifndef __REG_DEF_CHIP_H_ */

