/**
 * \file    reg_def_wdt.h
 * \brief   Register definition file
 * 
 * \par     Copyright (c) 2019 UWE Technologies Corp., Ltd. All Rights Reserved.
 * \author  James
 * \date    2019-04-26
 * \version 
 * 
 * \history 
 *  Date        Note
 *  2019-04-26  Original Creation
 * 
 */

#ifndef __REG_DEF_WDT_H_
#define __REG_DEF_WDT_H_



#define WDT_LDCNT_REG                                   (0x40000E00)

/**
WDT_LOAD_COUNT, RW, reset value(0x0)
WDT Timer Load Counter register
*/
#ifndef WDT_LOAD_COUNT
#define WDT_LOAD_COUNT
#endif
#define WDT_LDCNT_REG_WDT_LOAD_COUNT                    (0x00)
#define WDT_LDCNT_REG_WDT_LOAD_COUNT_WTH                (0x20)
#define WDT_LDCNT_REG_WDT_LOAD_COUNT_FLDSET             (0xFFFFFFFF)
#define WDT_LDCNT_REG_WDT_LOAD_COUNT_FLDMSK             (0x00000000)


#define WDT_CURVAL_REG                                  (0x40000E04)

/**
WDT_CUR_VALUE, RO, reset value(0xFFFFFFFF)
WDT Timer current value register
*/
#ifndef WDT_CUR_VALUE
#define WDT_CUR_VALUE
#endif
#define WDT_CURVAL_REG_WDT_CUR_VALUE                    (0x00)
#define WDT_CURVAL_REG_WDT_CUR_VALUE_WTH                (0x20)
#define WDT_CURVAL_REG_WDT_CUR_VALUE_FLDSET             (0xFFFFFFFF)
#define WDT_CURVAL_REG_WDT_CUR_VALUE_FLDMSK             (0x00000000)


#define WDT_CTRL_REG                                    (0x40000E08)

/**
WDT_RST_RECORD, RO, reset value(0x0)
1'b1 : Indicate the watch dog timer timeout once occurred.
*/
#ifndef WDT_RST_RECORD
#define WDT_RST_RECORD
#endif
#define WDT_CTRL_REG_WDT_RST_RECORD                     (0x03)
#define WDT_CTRL_REG_WDT_RST_RECORD_WTH                 (0x01)
#define WDT_CTRL_REG_WDT_RST_RECORD_FLDSET              (0x00000008)
#define WDT_CTRL_REG_WDT_RST_RECORD_FLDMSK              (0xFFFFFFF7)

/**
WDT_INT_MASK, RW, reset value(0x0)
WDT Timer interrupt mask bit,  1: Interrupt is masked; 0:Interrupt is not masked.
*/
#ifndef WDT_INT_MASK
#define WDT_INT_MASK
#endif
#define WDT_CTRL_REG_WDT_INT_MASK                       (0x02)
#define WDT_CTRL_REG_WDT_INT_MASK_WTH                   (0x01)
#define WDT_CTRL_REG_WDT_INT_MASK_FLDSET                (0x00000004)
#define WDT_CTRL_REG_WDT_INT_MASK_FLDMSK                (0xFFFFFFFB)

/**
WDT_MODE, RW, reset value(0x0)
0: Free run mode, reload value is 32'hFFFF_FFFF; 1: reload value is from WDT_LDCNT_REG.
*/
#ifndef WDT_MODE
#define WDT_MODE
#endif
#define WDT_CTRL_REG_WDT_MODE                           (0x01)
#define WDT_CTRL_REG_WDT_MODE_WTH                       (0x01)
#define WDT_CTRL_REG_WDT_MODE_FLDSET                    (0x00000002)
#define WDT_CTRL_REG_WDT_MODE_FLDMSK                    (0xFFFFFFFD)

/**
WDT_ENA, RW, reset value(0x0)
1: WDT Timer is enabled; 0: WDT Timer is disabled. WDT feed need to write 0 and write 1 to re-enable timer
*/
#ifndef WDT_ENA
#define WDT_ENA
#endif
#define WDT_CTRL_REG_WDT_ENA                            (0x00)
#define WDT_CTRL_REG_WDT_ENA_WTH                        (0x01)
#define WDT_CTRL_REG_WDT_ENA_FLDSET                     (0x00000001)
#define WDT_CTRL_REG_WDT_ENA_FLDMSK                     (0xFFFFFFFE)


#define WDT_EOI_REG                                     (0x40000E0C)

/**
WDT_EOI, RO, reset value(0x0)
Read this register will clear the interrupt of timer.
*/
#ifndef WDT_EOI
#define WDT_EOI
#endif
#define WDT_EOI_REG_WDT_EOI                             (0x00)
#define WDT_EOI_REG_WDT_EOI_WTH                         (0x20)
#define WDT_EOI_REG_WDT_EOI_FLDSET                      (0xFFFFFFFF)
#define WDT_EOI_REG_WDT_EOI_FLDMSK                      (0x00000000)


#define WDT_INT_STATUS_REG                              (0x40000E10)

/**
WDT_INT_STATUS, RO, reset value(0x0)
WDT Timer interrupt status register. Will be masked by WDT_INT_MASK bit.
*/
#ifndef WDT_INT_STATUS
#define WDT_INT_STATUS
#endif
#define WDT_INT_STATUS_REG_WDT_INT_STATUS               (0x00)
#define WDT_INT_STATUS_REG_WDT_INT_STATUS_WTH           (0x01)
#define WDT_INT_STATUS_REG_WDT_INT_STATUS_FLDSET        (0x00000001)
#define WDT_INT_STATUS_REG_WDT_INT_STATUS_FLDMSK        (0xFFFFFFFE)


#define WDT_INT_RAWSTATUS_REG                           (0x40000E14)

/**
WDT_INT_RAW_STATUS, RO, reset value(0x0)
WDT Timer interrupt raw status register.
*/
#ifndef WDT_INT_RAW_STATUS
#define WDT_INT_RAW_STATUS
#endif
#define WDT_INT_RAWSTATUS_REG_WDT_INT_RAW_STATUS        (0x00)
#define WDT_INT_RAWSTATUS_REG_WDT_INT_RAW_STATUS_WTH    (0x01)
#define WDT_INT_RAWSTATUS_REG_WDT_INT_RAW_STATUS_FLDSET (0x00000001)
#define WDT_INT_RAWSTATUS_REG_WDT_INT_RAW_STATUS_FLDMSK (0xFFFFFFFE)



#endif /* #ifndef __REG_DEF_WDT_H_ */

