/***********************************************************************************************************
 * Copyright (c)  2017 - 2020, Unicmicro Co.,Ltd .
 * All rights reserved.
 * Filename    : um321xA.h
 * Description : um321xA addr header file
 * Author(s)   : will
 * version     : V1.0
 * Modify date : 2020-11-10
 ***********************************************************************************************************/
#ifndef __UM321XA_H__
#define __UM321XA_H__

#undef NULL
#define NULL 0                   /* see <stddef.h> */

/* --------------------  Configuration of the Cortex-M0 Processor and Core Peripherals  ------------------ */
#define __CM0_REV                 					0x0000U   												/* Core revision r0p0 */
#define __MPU_PRESENT             					0         												/* MPU present or not */
#define __VTOR_PRESENT            					0         												/* no VTOR present*/
#define __NVIC_PRIO_BITS          					2         												/* Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig    					0         												/* Set to 1 if different SysTick Config is used */

/* ------------------------------  Interrupt Number Definition  ------------------------------------------ */
typedef enum IRQn
{
	/* --------------------------  Cortex-M0 Processor Exceptions Numbers  ------------------------------- */
	NonMaskableInt_IRQn			  					= -14,      											/* 2 Non Maskable Interrupt */
	HardFault_IRQn                					= -13,      											/* 3 HardFault Interrupt */
	SVCall_IRQn                   					= -5,      												/* 11 SV Call Interrupt */
	PendSV_IRQn                   					= -2,      												/* 14 Pend SV Interrupt */
	SysTick_IRQn                  					= -1,      												/* 15 System Tick Interrupt */

	/* --------------------------  ARMCM0 Specific Interrupt Numbers  ------------------------------------ */
	GPIO_PA_IRQn				  					= 0,        											/* 0:  GPIO_PA_IRQHandler */
	GPIO_PB_IRQn				  					= 1,        											/* 1:  GPIO_PB_IRQHandler */
	GPIO_PC_IRQn				  					= 2,        											/* 2:  GPIO_PC_IRQHandler */
	GPIO_PD_IRQn		          					= 3,        											/* 3:  GPIO_PD_IRQHandler */
	DMA_IRQn		          	  					= 4,        											/* 4:  DMA_IRQHandler */
	LPTIMER1_IRQn                    				= 5,        											/* 5:  LPTIMER1_IRQHandler */
	UART0_IRQn                    					= 6,        											/* 6:  UART0_IRQHandler */
	LPUART_IRQn	                  					= 7,        											/* 7:  LPUART_IRQHandler */
	UART1_IRQn                    					= 8,        											/* 8:  UART1_IRQHandler */
	I2C_IRQn                      					= 9,        											/* 9:  I2C_IRQHandler */
	SPI0_IRQn                     					= 10,       											/* 10: SPI0_IRQHandler */
	SPI1_IRQn                     					= 11,       											/* 11: SPI1_IRQHandler */
	CAN_IRQn                     					= 12,       											/* 12: CAN_IRQHandler */
	VREF_IRQn                     					= 13,       											/* 13: VREF_IRQHandler */    
	GTIMER0_IRQn		          					= 14,       											/* 14: GTIMER0_IRQHandler */
	GTIMER1_IRQn	              					= 15,       											/* 15: GTIMER1_IRQHandler */
	GTIMER2_IRQn	              					= 16,       											/* 16: GTIMER2_IRQHandler */
	QSPI_IRQn                  						= 17,       											/* 17: QSPI_IRQHandler */
	LPTIMER0_IRQn                  					= 18,       											/* 18: LPTIMER0_IRQHandler */	 
	COMP0_IRQn                  					= 19,       											/* 19: COMP0_IRQHandler */	
	GPIO_PE_IRQn                  					= 20,       											/* 20: GPIO_PE_IRQHandler */	
	COMP1_IRQn                  					= 21,       											/* 21: COMP1_IRQHandler */	    
	WDT_IRQn                  	  					= 22,       											/* 22: WDT_IRQHandler */
	RTC_IRQn                  	  					= 23,       											/* 23: RTC_IRQHandler */
	ADC_IRQn                      					= 24,       											/* 24: ADC_IRQHandler */
	LPTIMER2_IRQn                    				= 25,        											/* 25: LPTIMER2_IRQHandler */
    COMP2_IRQn                    				    = 26,        											/* 26: COMP2_IRQHandler */
	WWDT_IRQn                    					= 27,        											/* 27: WWDT_IRQHandler */
	VDT_IRQn                 	  					= 28,       											/* 28: VDT_IRQHandler */
	OPA_IRQn                 	  					= 29,       											/* 29: OPA_IRQHandler */
	FLASH_IRQn                    					= 30        											/* 30: FLASH_IRQHandler */
} IRQn_Type;

//#include  "core_cm0plus.h"
#include  <core_cm0plus.h>

/***********************************************************************************************************/
/*                            Device Specific Peripheral Section                                           */
/***********************************************************************************************************/

/*------------------------------ EFC -----------------------------------------*/
#define EFC_BASE_ADDR			0x01100000
#define REG_EFC_CTRL    		(*(volatile uint32_t *)(EFC_BASE_ADDR + 0x00))		/* EFC 控制寄存器 */
#define REG_EFC_SEC    			(*(volatile uint32_t *)(EFC_BASE_ADDR + 0x04))		/* EFC 写擦安全寄存器 */
#define REG_EFC_STATUS    		(*(volatile uint32_t *)(EFC_BASE_ADDR + 0x08))		/* EFC 状态寄存器 */
#define REG_EFC_INTSTATUS   	(*(volatile uint32_t *)(EFC_BASE_ADDR + 0x0C))		/* EFC 中断状态寄存器 */
#define REG_EFC_INEN   			(*(volatile uint32_t *)(EFC_BASE_ADDR + 0x10))		/* EFC 中断使能寄存器 */
#define REG_EFC_HALFUS   		(*(volatile uint32_t *)(EFC_BASE_ADDR + 0x14))		/* EFC 时间标尺寄存器 */
#define REG_EFC_RCHTRIM   		(*(volatile uint32_t *)(EFC_BASE_ADDR + 0x20))		/* EFC RCH TRIM 寄存器 */
#define REG_EFC_RCLTRIM   		(*(volatile uint32_t *)(EFC_BASE_ADDR + 0x24))		/* EFC RCL TRIM 寄存器 */



/*------------------------------ QSPI ----------------------------------------*/
#define QSPI_BASE_ADDR			0x01100400
#define REG_QSPI_CTRL         	(*(volatile uint32_t *)(QSPI_BASE_ADDR + 0x00))		
#define REG_QSPI_BAUD          	(*(volatile uint32_t *)(QSPI_BASE_ADDR + 0x04))		
#define REG_QSPI_MEMO_ACC       (*(volatile uint32_t *)(QSPI_BASE_ADDR + 0x08))		
#define REG_QSPI_CMD         	(*(volatile uint32_t *)(QSPI_BASE_ADDR + 0x0C))		
#define REG_QSPI_PARA_R        	(*(volatile uint32_t *)(QSPI_BASE_ADDR + 0x10))		
#define REG_QSPI_PARA_W         (*(volatile uint32_t *)(QSPI_BASE_ADDR + 0x14))		
#define REG_QSPI_PGT_SET        (*(volatile uint32_t *)(QSPI_BASE_ADDR + 0x18))		
#define REG_QSPI_INTEN          (*(volatile uint32_t *)(QSPI_BASE_ADDR + 0x1C))		
#define REG_QSPI_INTUS          (*(volatile uint32_t *)(QSPI_BASE_ADDR + 0x20))		
#define REG_QSPI_STATUS     	(*(volatile uint32_t *)(QSPI_BASE_ADDR + 0x24))	
#define REG_QSPI_RXBUF          (*(volatile uint32_t *)(QSPI_BASE_ADDR + 0x28))	

/*------------------------------ UART0 -------------------------------------------------*/
#define UART0_BASE_ADDR			0x40000000
#define REG_UART0_ISR			(*(volatile uint32_t *)(UART0_BASE_ADDR + 0x00))	/* UART0 中断状态寄存器 */
#define REG_UART0_IER			(*(volatile uint32_t *)(UART0_BASE_ADDR + 0x04))	/* UART0 中断使能寄存器 */
#define REG_UART0_CR			(*(volatile uint32_t *)(UART0_BASE_ADDR + 0x08))	/* UART0 控制寄存器 */
#define REG_UART0_TDR			(*(volatile uint32_t *)(UART0_BASE_ADDR + 0x0C))	/* UART0 发送数据寄存器 */
#define REG_UART0_RDR			(*(volatile uint32_t *)(UART0_BASE_ADDR + 0x0C))	/* UART0 接收数据寄存器 */
#define REG_UART0_BRPL			(*(volatile uint32_t *)(UART0_BASE_ADDR + 0x10))	/* UART0 波特率参数低位寄存器 */
#define REG_UART0_BRPH			(*(volatile uint32_t *)(UART0_BASE_ADDR + 0x14))	/* UART0 波特率参数高位寄存器 */

/*------------------------------- LPUART -------------------------------------------------*/
#define LPUART_BASE_ADDR		0x40000400
#define REG_LPUART_LPURXD		(*(volatile uint32_t *)(LPUART_BASE_ADDR + 0x00))	/* LPUART 接收数据寄存器 */
#define REG_LPUART_LPUTXD		(*(volatile uint32_t *)(LPUART_BASE_ADDR + 0x04))	/* LPUART 发送数据寄存器 */
#define REG_LPUART_LPUSTA		(*(volatile uint32_t *)(LPUART_BASE_ADDR + 0x08))	/* LPUART 状态寄存器 */
#define REG_LPUART_LPUCON		(*(volatile uint32_t *)(LPUART_BASE_ADDR + 0x0C))	/* LPUART 控制寄存器 */
#define REG_LPUART_LPUIF		(*(volatile uint32_t *)(LPUART_BASE_ADDR + 0x10))	/* LPUART 中断标志寄存器 */
#define REG_LPUART_LPUBAUD		(*(volatile uint32_t *)(LPUART_BASE_ADDR + 0x14))	/* LPUART 波特率寄存器 */
#define REG_LPUART_LPUEN		(*(volatile uint32_t *)(LPUART_BASE_ADDR + 0x18))	/* LPUART 接收使能寄存器 */
#define REG_LPUART_COMPARE		(*(volatile uint32_t *)(LPUART_BASE_ADDR + 0x1C))	/* LPUART 数据匹配寄存器 */
#define REG_LPUART_MODU			(*(volatile uint32_t *)(LPUART_BASE_ADDR + 0x20))	/* LPUART 波特率调制控制寄存器 */

/*------------------------------ SPI0 --------------------------------------------------*/
#define SPI0_BASE_ADDR			0x40000800
#define REG_SPI0_SPICR          (*(volatile uint32_t *)(SPI0_BASE_ADDR + 0x00))		/* SPI0 配置寄存器 */
#define REG_SPI0_SPICS0         (*(volatile uint32_t *)(SPI0_BASE_ADDR + 0x04))		/* SPI0 主模式控制寄存器0 */
#define REG_SPI0_SPICS1         (*(volatile uint32_t *)(SPI0_BASE_ADDR + 0x08))		/* SPI0 主模式控制寄存器1 */
#define REG_SPI0_SPIOPCR        (*(volatile uint32_t *)(SPI0_BASE_ADDR + 0x14))		/* SPI0 过程控制寄存器 */
#define REG_SPI0_SPIIE          (*(volatile uint32_t *)(SPI0_BASE_ADDR + 0x18))		/* SPI0 中断控制寄存器 */
#define REG_SPI0_SPIIF          (*(volatile uint32_t *)(SPI0_BASE_ADDR + 0x1C))		/* SPI0 中断标志寄存器 */
#define REG_SPI0_SPITXBUF       (*(volatile uint32_t *)(SPI0_BASE_ADDR + 0x20))		/* SPI0 发送缓存寄存器 */
#define REG_SPI0_SPIRXBUF       (*(volatile uint32_t *)(SPI0_BASE_ADDR + 0x24))		/* SPI0 接收缓存寄存器 */
#define REG_SPI0_DMA_SPIRX_LEV  (*(volatile uint32_t *)(SPI0_BASE_ADDR + 0x28))		/* SPI0 DMA接收设置寄存器 */
#define REG_SPI0_DMA_SPITX_LEV  (*(volatile uint32_t *)(SPI0_BASE_ADDR + 0x2C))		/* SPI0 DMA发送设置寄存器 */


/*------------------------------ GTIMER0 ------------------------------------------------*/
#define GTIMER0_BASE_ADDR		0x40000C00
#define REG_GTIM0_CR			(*(volatile uint32_t *)(GTIMER0_BASE_ADDR + 0x00))	/* Timer0 控制寄存器 */	
#define REG_GTIM0_IER			(*(volatile uint32_t *)(GTIMER0_BASE_ADDR + 0x04))	/* Timer0 中断使能寄存器 */
#define REG_GTIM0_SR			(*(volatile uint32_t *)(GTIMER0_BASE_ADDR + 0x08))	/* Timer0 状态寄存器 */
#define REG_GTIM0_EGR			(*(volatile uint32_t *)(GTIMER0_BASE_ADDR + 0x0C))	/* Timer0 事件产生寄存器 */
#define REG_GTIM0_CCMR			(*(volatile uint32_t *)(GTIMER0_BASE_ADDR + 0x10))	/* Timer0 捕捉/比较寄存器 */
#define REG_GTIM0_CCER			(*(volatile uint32_t *)(GTIMER0_BASE_ADDR + 0x14))	/* Timer0 捕捉/比较使能寄存器 */
#define REG_GTIM0_CNT			(*(volatile uint32_t *)(GTIMER0_BASE_ADDR + 0x18))	/* Timer0 计数器寄存器 */
#define REG_GTIM0_PSC			(*(volatile uint32_t *)(GTIMER0_BASE_ADDR + 0x1C))	/* Timer0 预分频寄存器 */
#define REG_GTIM0_ARR			(*(volatile uint32_t *)(GTIMER0_BASE_ADDR + 0x20))	/* Timer0 自动重载寄存器 */
#define REG_GTIM0_CCR			(*(volatile uint32_t *)(GTIMER0_BASE_ADDR + 0x24))	/* Timer0 捕捉/比较寄存器 */
#define REG_GTIM0_CARS1			(*(volatile uint32_t *)(GTIMER0_BASE_ADDR + 0x28))	/* Timer0 捕捉/比较寄存器 */ 

/*------------------------------ LPTIMER0 -----------------------------------------------*/
#define LPTIMER0_BASE_ADDR		0x40001000
#define REG_LPTIM0_LPTCFG		(*(volatile uint32_t *)(LPTIMER0_BASE_ADDR + 0x00))	/* LPTIM0 配置寄存器 */
#define REG_LPTIM0_LPTCNT		(*(volatile uint32_t *)(LPTIMER0_BASE_ADDR + 0x04))	/* LPTIM0 计数寄存器 */
#define REG_LPTIM0_LPTCMP		(*(volatile uint32_t *)(LPTIMER0_BASE_ADDR + 0x08))	/* LPTIM0 比较值寄存器 */
#define REG_LPTIM0_LPTTARGET	(*(volatile uint32_t *)(LPTIMER0_BASE_ADDR + 0x0C))	/* LPTIM0 目标值寄存器 */
#define REG_LPTIM0_LPTIE		(*(volatile uint32_t *)(LPTIMER0_BASE_ADDR + 0x10))	/* LPTIM0 中断使能寄存器 */
#define REG_LPTIM0_LPTIF		(*(volatile uint32_t *)(LPTIMER0_BASE_ADDR + 0x14))	/* LPTIM0 中断标志寄存器 */
#define REG_LPTIM0_LPTCTRL		(*(volatile uint32_t *)(LPTIMER0_BASE_ADDR + 0x18))	/* LPTIM0 控制寄存器 */


/*-------------------------------- RTC ---------------------------------------------------*/
#define RTC_BASE_ADDR			0x40001400
#define REG_RTC_RTCWE           (*(volatile uint32_t *)(RTC_BASE_ADDR + 0x00))		/* RTC 写使能寄存器 */
#define REG_RTC_RTCIE           (*(volatile uint32_t *)(RTC_BASE_ADDR + 0x04))		/* RTC 中断使能寄存器 */
#define REG_RTC_RTCIF           (*(volatile uint32_t *)(RTC_BASE_ADDR + 0x08))		/* RTC 中断标志寄存器 */
#define REG_RTC_BCDSEC          (*(volatile uint32_t *)(RTC_BASE_ADDR + 0x0C))		/* RTC BCD时间秒寄存器 */
#define REG_RTC_BCDMIN          (*(volatile uint32_t *)(RTC_BASE_ADDR + 0x10))		/* RTC BCD时间分钟寄存器 */
#define REG_RTC_BCDHOUR         (*(volatile uint32_t *)(RTC_BASE_ADDR + 0x14))		/* RTC BCD时间小时寄存器 */
#define REG_RTC_BCDDATE         (*(volatile uint32_t *)(RTC_BASE_ADDR + 0x18))		/* RTC BCD时间天寄存器 */
#define REG_RTC_BCDWEEK         (*(volatile uint32_t *)(RTC_BASE_ADDR + 0x1C))		/* RTC BCD时间星期寄存器 */
#define REG_RTC_BCDMONTH        (*(volatile uint32_t *)(RTC_BASE_ADDR + 0x20))		/* RTC BCD时间月寄存器 */
#define REG_RTC_BCDYEAR         (*(volatile uint32_t *)(RTC_BASE_ADDR + 0x24))		/* RTC BCD时间年寄存器 */
#define REG_RTC_ALARM           (*(volatile uint32_t *)(RTC_BASE_ADDR + 0x28))		/* RTC 闹钟寄存器 */
#define REG_RTC_FSEL            (*(volatile uint32_t *)(RTC_BASE_ADDR + 0x2C))		/* RTC 时钟信号输出控制寄存器 */
#define REG_RTC_ADJUST          (*(volatile uint32_t *)(RTC_BASE_ADDR + 0x30))		/* RTC LTBC数值调整寄存器 */
#define REG_RTC_ADSIGN          (*(volatile uint32_t *)(RTC_BASE_ADDR + 0x34))		/* RTC LTBC数值调整方向寄存器 */	
#define REG_RTC_PRISEN          (*(volatile uint32_t *)(RTC_BASE_ADDR + 0x38))		/* RTC LTBC虚拟调校使能寄存器 */
#define REG_RTC_SECCNT          (*(volatile uint32_t *)(RTC_BASE_ADDR + 0x3C))		/* RTC 毫秒计数寄存器 */
#define REG_RTC_STAMPEN         (*(volatile uint32_t *)(RTC_BASE_ADDR + 0x40))		/* RTC 时间戳使能寄存器 */
#define REG_RTC_CLKSTAMP0R      (*(volatile uint32_t *)(RTC_BASE_ADDR + 0x44))		/* RTC 上升沿时间戳寄存器0 */
#define REG_RTC_CALSTAMP0R      (*(volatile uint32_t *)(RTC_BASE_ADDR + 0x48))		/* RTC 上升沿日历戳寄存器0 */
#define REG_RTC_CLKSTAMP0F      (*(volatile uint32_t *)(RTC_BASE_ADDR + 0x4C))		/* RTC 下降沿时间戳寄存器0 */	
#define REG_RTC_CALSTAMP0F      (*(volatile uint32_t *)(RTC_BASE_ADDR + 0x50))		/* RTC 下降沿日历戳寄存器0 */
#define REG_RTC_CLKSTAMP1R      (*(volatile uint32_t *)(RTC_BASE_ADDR + 0x54))		/* RTC 上升沿时间戳寄存器1 */
#define REG_RTC_CALSTAMP1R      (*(volatile uint32_t *)(RTC_BASE_ADDR + 0x58))      /* RTC 上升沿日历戳寄存器1 */
#define REG_RTC_CLKSTAMP1F      (*(volatile uint32_t *)(RTC_BASE_ADDR + 0x5C))      /* RTC 下降沿时间戳寄存器1 */
#define REG_RTC_CALSTAMP1F      (*(volatile uint32_t *)(RTC_BASE_ADDR + 0x60))      /* RTC 下降沿日历戳寄存器1 */


/*------------------------------ CRC ---------------------------------------------------*/
#define CRC16_BASE_ADDR			0x40001800
#define REG_CRC16_DATA          (*(volatile uint32_t *)(CRC16_BASE_ADDR + 0x00))	/* CRC数据寄存器 */
#define REG_CRC16_INIT          (*(volatile uint32_t *)(CRC16_BASE_ADDR + 0x04))	/* CRC初始值寄存器 */
#define REG_CRC16_CTRL          (*(volatile uint32_t *)(CRC16_BASE_ADDR + 0x08))	/* CRC控制寄存器 */


/*-------------------------------- ADC ----------------------------------------------*/
#define ADC_0					0
#define ADC_1					1
#define ADC_2					2
#define ADC_3					3
#define ADC_4					4
#define ADC_5					5
#define ADC_6					6
#define ADC_7					7



#define ADC_BASE_ADDR			0x40001C00
#define REG_ADC_GCR             (*(volatile uint32_t *)(ADC_BASE_ADDR + 0x00))		/*ADC 总控寄存器 */
#define REG_ADC_DR(x)			(*(volatile uint32_t *)(ADC_BASE_ADDR + (0x04*(x)+0x04) ))		/*ADC 通道0数据寄存器 */
	
#define REG_ADC_CDR             (*(volatile uint32_t *)(ADC_BASE_ADDR + 0x24))		/*ADC 时钟分频寄存器 */
#define REG_ADC_ISR             (*(volatile uint32_t *)(ADC_BASE_ADDR + 0x28))		/*ADC 中断状态寄存器 */
#define REG_ADC_IER             (*(volatile uint32_t *)(ADC_BASE_ADDR + 0x2C))		/*ADC 中断使能寄存器 */
#define REG_ADC_ICR             (*(volatile uint32_t *)(ADC_BASE_ADDR + 0x30))		/*ADC 中断清除寄存器 */
#define REG_ADC_COUNT           (*(volatile uint32_t *)(ADC_BASE_ADDR + 0x34))		/*ADC 转换间隔寄存器 */
#define REG_ADC_RXREG           (*(volatile uint32_t *)(ADC_BASE_ADDR + 0x38))		/*ADC 接收数据寄存器 */
#define REG_ADC_CSTAT           (*(volatile uint32_t *)(ADC_BASE_ADDR + 0x3C))		/*ADC 状态寄存器 */
#define REG_ADC_SPW		        (*(volatile uint32_t *)(ADC_BASE_ADDR + 0x40))		/*ADC 采样时钟脉宽寄存器 */
#define REG_ADC_TCRL		    (*(volatile uint32_t *)(ADC_BASE_ADDR + 0x44))		/*ADC 模拟配置寄存器 */
#define REG_ADC_HDT		        (*(volatile uint32_t *)(ADC_BASE_ADDR + 0x48))		/*ADC 硬件触发使能配置寄存器 */	

/*------------------------------- SYSREG ------------------------------------------------*/
#define SCU_BASE_ADDR			0x40002000
#define REG_SCU_CTRL0			(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x00))		/* 系统控制寄存器0 */
#define REG_SCU_CTRL1			(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x04))		/* 系统控制寄存器1 */
#define REG_SCU_CTRLPROTECT		(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x08))		/* 系统控制保护寄存器 */
#define REG_SCU_OSCCTRL			(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x0C))		/* 时钟控制寄存器 */
#define REG_SCU_PERICLKEN		(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x10))		/* 外围模块时钟寄存器 */
#define REG_SCU_RESETFLAG		(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x20))		/* 复位标识寄存器 */
#define REG_SCU_PERIRESET		(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x24))		/* 外围模块复位控制寄存器 */
#define REG_SCU_EXTRESETCTRL	        (*(volatile uint32_t *)(SCU_BASE_ADDR + 0x28))		/* 外部复位滤波控制寄存器 */
#define REG_SCU_PASEL			(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x30))		/* 端口PA功能配置寄存器 */
#define REG_SCU_PBSEL			(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x34))		/* 端口PB功能配置寄存器 */
#define REG_SCU_PCSEL			(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x38))		/* 端口PC功能配置寄存器 */
#define REG_SCU_PDSEL			(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x3C))		/* 端口PD功能配置寄存器 */
#define REG_SCU_PESEL			(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x40))      /* 端口PE功能配置寄存器 */
#define REG_SCU_PADADS			(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x44))		/* 端口数模配置寄存器 */
#define REG_SCU_PADDR0			(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x48))		/* 端口驱动能力配置寄存器0 */
#define REG_SCU_PADDR1			(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x4C))      /* 端口驱动能力配置寄存器1 */
#define REG_SCU_PADPU0			(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x50))		/* 端口上拉配置寄存器0 */
#define REG_SCU_PADPU1			(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x54))      /* 端口上拉配置寄存器1 */
#define REG_SCU_PADPD0			(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x58))		/* 端口下拉配置寄存器0 */
#define REG_SCU_PADPD1			(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x5C))      /* 端口下拉配置寄存器1 */
#define REG_SCU_PADOD0			(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x60))		/* 端口开漏输出配置寄存器0 */
#define REG_SCU_PADOD1			(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x64))      /* 端口开漏输出配置寄存器1 */
#define REG_SCU_PADCS0			(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x68))		/* 端口输入类型配置寄存器0 */
#define REG_SCU_PADCS1			(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x6C))      /* 端口输入类型配置寄存器1 */
#define REG_SCU_PADIE0			(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x70))		/* 端口输入配置寄存器0 */
#define REG_SCU_PADIE1			(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x74))      /* 端口输入配置寄存器1 */
#define REG_SCU_PADSR0			(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x78))      /* 端口速率配置寄存器0 */
#define REG_SCU_PADSR1			(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x7C))      /* 端口速率配置寄存器1 */
#define REG_SCU_IOCTRLPROTECT	(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x80))		/* IO控制保护寄存器 */
#define REG_SCU_LVDCFG			(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x84))		/* LVD控制寄存器 */
#define REG_SCU_OPACFG			(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x88))      /* OPA控制寄存器 */
#define REG_SCU_CMPCFG			(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x8C))      /* CMP控制寄存器 */
#define REG_SCU_EXTRSTSEL		(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x90))		/* 外部复位端口选择寄存器 */
#define REG_SCU_STOPMODESEL		(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x94))		/* 停止模式选择寄存器 */
#define REG_SCU_REMAP			(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x98))		/* REMAP寄存器 */
#define REG_SCU_VECTOROFFSET	(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x9C))		/* 中断向量地址重映射寄存器 */
#define REG_SCU_HRNGCR			(*(volatile uint32_t *)(SCU_BASE_ADDR + 0xA0))		/* 随机数控制寄存器 */
#define REG_SCU_HRNGSEED		(*(volatile uint32_t *)(SCU_BASE_ADDR + 0xA4))		/* 随机数种子寄存器 */
#define REG_SCU_HRNGDATA		(*(volatile uint32_t *)(SCU_BASE_ADDR + 0xA8))		/* 随机数数据寄存器 */	
#define REG_SCU_BUZZERCR		(*(volatile uint32_t *)(SCU_BASE_ADDR + 0xAC))		/* 蜂鸣器控制寄存器/BUZERCR */
#define REG_SCU_LVRCFG			(*(volatile uint32_t *)(SCU_BASE_ADDR + 0xB0))      /* LVR控制寄存器 */
#define REG_SCU_VREFCFG			(*(volatile uint32_t *)(SCU_BASE_ADDR + 0xB4))      /* VREF控制寄存器 */
#define REG_SCU_XTHCFG			(*(volatile uint32_t *)(SCU_BASE_ADDR + 0xB8))      /* XTH控制寄存器 */
#define REG_SCU_COMP0STATUS		(*(volatile uint32_t *)(SCU_BASE_ADDR + 0xBC))      /* COMP0状态寄存器 */
#define REG_SCU_COMP1STATUS		(*(volatile uint32_t *)(SCU_BASE_ADDR + 0xC0))      /* 比较器0状态寄存器 */
#define REG_SCU_COMP2STATUS		(*(volatile uint32_t *)(SCU_BASE_ADDR + 0xC4))      /* 比较器1状态寄存器 */
#define REG_SCU_OPASTATUS		(*(volatile uint32_t *)(SCU_BASE_ADDR + 0xC8))      /* 比较器2状态寄存器 */
#define REG_SCU_VREFSTATUS		(*(volatile uint32_t *)(SCU_BASE_ADDR + 0xCC))      /* VREF状态寄存器 */ 
    
/*----------------------------- WDT ---------------------------------------------------*/
#define WDT_BASE_ADDR			0x40002400
#define REG_WDT_LOAD			(*(volatile uint32_t *)(WDT_BASE_ADDR + 0x00))		/* WDT 装载寄存器 */
#define REG_WDT_CNT				(*(volatile uint32_t *)(WDT_BASE_ADDR + 0x04))		/* WDT 计数寄存器 */
#define REG_WDT_CTRL			(*(volatile uint32_t *)(WDT_BASE_ADDR + 0x08))		/* WDT 控制寄存器 */
#define REG_WDT_CLR				(*(volatile uint32_t *)(WDT_BASE_ADDR + 0x0C))		/* WDT 清除寄存器 */
#define REG_WDT_INTRAW			(*(volatile uint32_t *)(WDT_BASE_ADDR + 0x10))		/* WDT RAW中断状态寄存器 */
#define REG_WDT_MINTS			(*(volatile uint32_t *)(WDT_BASE_ADDR + 0x14))		/* WDT MASK中断状态寄存器 */
#define REG_WDT_STALL			(*(volatile uint32_t *)(WDT_BASE_ADDR + 0x18))		/* WDT STALL寄存器 */
#define REG_WDT_LOCK			(*(volatile uint32_t *)(WDT_BASE_ADDR + 0x1C))		/* WDT LOCK寄存器 */

/*----------------------------- LPTIMER1 -----------------------------------------------*/
#define LPTIMER1_BASE_ADDR		0x40002800
#define REG_LPTIM1_LPTCFG		(*(volatile uint32_t *)(LPTIMER1_BASE_ADDR + 0x00))	/* LPTIM1 配置寄存器 */
#define REG_LPTIM1_LPTCNT		(*(volatile uint32_t *)(LPTIMER1_BASE_ADDR + 0x04))	/* LPTIM1 计数寄存器 */
#define REG_LPTIM1_LPTCMP		(*(volatile uint32_t *)(LPTIMER1_BASE_ADDR + 0x08))	/* LPTIM1 比较值寄存器 */
#define REG_LPTIM1_LPTTARGET	(*(volatile uint32_t *)(LPTIMER1_BASE_ADDR + 0x0C))	/* LPTIM1 目标值寄存器 */
#define REG_LPTIM1_LPTIE		(*(volatile uint32_t *)(LPTIMER1_BASE_ADDR + 0x10))	/* LPTIM1 中断使能寄存器 */
#define REG_LPTIM1_LPTIF		(*(volatile uint32_t *)(LPTIMER1_BASE_ADDR + 0x14))	/* LPTIM1 中断标志寄存器 */
#define REG_LPTIM1_LPTCTRL		(*(volatile uint32_t *)(LPTIMER1_BASE_ADDR + 0x18))	/* LPTIM1 控制寄存器 */

/*----------------------------- LPTIMER2 -----------------------------------------------*/
#define LPTIMER2_BASE_ADDR		0x40002C00
#define REG_LPTIM2_LPTCFG		(*(volatile uint32_t *)(LPTIMER2_BASE_ADDR + 0x00))	/* LPTIM2 配置寄存器 */
#define REG_LPTIM2_LPTCNT		(*(volatile uint32_t *)(LPTIMER2_BASE_ADDR + 0x04))	/* LPTIM2 计数寄存器 */
#define REG_LPTIM2_LPTCMP		(*(volatile uint32_t *)(LPTIMER2_BASE_ADDR + 0x08))	/* LPTIM2 比较值寄存器 */
#define REG_LPTIM2_LPTTARGET	(*(volatile uint32_t *)(LPTIMER2_BASE_ADDR + 0x0C))	/* LPTIM2 目标值寄存器 */
#define REG_LPTIM2_LPTIE		(*(volatile uint32_t *)(LPTIMER2_BASE_ADDR + 0x10))	/* LPTIM2 中断使能寄存器 */
#define REG_LPTIM2_LPTIF		(*(volatile uint32_t *)(LPTIMER2_BASE_ADDR + 0x14))	/* LPTIM2 中断标志寄存器 */
#define REG_LPTIM2_LPTCTRL		(*(volatile uint32_t *)(LPTIMER2_BASE_ADDR + 0x18))	/* LPTIM2 控制寄存器 */
	


/*----------------------------- UART1 -------------------------------------------------*/
#define UART1_BASE_ADDR			0x40003000
#define REG_UART1_RBR			(*(volatile uint32_t *)(UART1_BASE_ADDR + 0x00))	/* UART1 接收缓冲寄存器 */
#define REG_UART1_THR			(*(volatile uint32_t *)(UART1_BASE_ADDR + 0x00))	/* UART1 发送缓冲寄存器 */
#define REG_UART1_DLL			(*(volatile uint32_t *)(UART1_BASE_ADDR + 0x00))	/* UART1 波特率分频低位寄存器 */	
#define REG_UART1_DLH			(*(volatile uint32_t *)(UART1_BASE_ADDR + 0x04))	/* UART1 波特率分频高位寄存器 */
#define REG_UART1_IER			(*(volatile uint32_t *)(UART1_BASE_ADDR + 0x04))	/* UART1 中断使能寄存器 */
#define REG_UART1_IIR			(*(volatile uint32_t *)(UART1_BASE_ADDR + 0x08))	/* UART1 中断状态寄存器 */
#define REG_UART1_FCR			(*(volatile uint32_t *)(UART1_BASE_ADDR + 0x08))	/* UART1 FIFO控制寄存器 */
#define REG_UART1_LCR			(*(volatile uint32_t *)(UART1_BASE_ADDR + 0x0C))	/* UART1 LINE控制寄存器 */
#define REG_UART1_MCR			(*(volatile uint32_t *)(UART1_BASE_ADDR + 0x10))	/* UART1 流控制寄存器 */
#define REG_UART1_LSR			(*(volatile uint32_t *)(UART1_BASE_ADDR + 0x14))	/* UART1 LINE中断状态寄存器 */
#define REG_UART1_MSR			(*(volatile uint32_t *)(UART1_BASE_ADDR + 0x18))	/* UART1 流状态寄存器 */	
#define REG_UART1_USR			(*(volatile uint32_t *)(UART1_BASE_ADDR + 0x7C))	/* UART1 状态寄存器 */
#define REG_UART1_TFL			(*(volatile uint32_t *)(UART1_BASE_ADDR + 0x80))	/* UART1 发送FIFO数据个数寄存器 */	
#define REG_UART1_RFL			(*(volatile uint32_t *)(UART1_BASE_ADDR + 0x84))	/* UART1 接收FIFO数据个数寄存器 */	
#define REG_UART1_DLF			(*(volatile uint32_t *)(UART1_BASE_ADDR + 0xC0))	/* UART1 小数分频寄存器 */
#define REG_UART1_RAR			(*(volatile uint32_t *)(UART1_BASE_ADDR + 0xC4))	/* UART1 接收地址匹配寄存器 */
#define REG_UART1_TAR			(*(volatile uint32_t *)(UART1_BASE_ADDR + 0xC8))	/* UART1 发送地址匹配寄存器 */
#define REG_UART1_LCRE			(*(volatile uint32_t *)(UART1_BASE_ADDR + 0xCC))	/* UART1 LINE控制扩展寄存器 */

/*----------------------------- GTIMER1 ------------------------------------------------*/
#define GTIMER1_BASE_ADDR		0x40003400
#define REG_GTIM1_CR			(*(volatile uint32_t *)(GTIMER1_BASE_ADDR + 0x00))	/* Timer1 控制寄存器 */	
#define REG_GTIM1_IER			(*(volatile uint32_t *)(GTIMER1_BASE_ADDR + 0x04))	/* Timer1 中断使能寄存器 */
#define REG_GTIM1_SR			(*(volatile uint32_t *)(GTIMER1_BASE_ADDR + 0x08))	/* Timer1 状态寄存器 */
#define REG_GTIM1_EGR			(*(volatile uint32_t *)(GTIMER1_BASE_ADDR + 0x0C))	/* Timer1 事件产生寄存器 */
#define REG_GTIM1_CCMR			(*(volatile uint32_t *)(GTIMER1_BASE_ADDR + 0x10))	/* Timer1 捕捉/比较寄存器 */
#define REG_GTIM1_CCER			(*(volatile uint32_t *)(GTIMER1_BASE_ADDR + 0x14))	/* Timer1 捕捉/比较使能寄存器 */
#define REG_GTIM1_CNT			(*(volatile uint32_t *)(GTIMER1_BASE_ADDR + 0x18))	/* Timer1 计数器寄存器 */
#define REG_GTIM1_PSC			(*(volatile uint32_t *)(GTIMER1_BASE_ADDR + 0x1C))	/* Timer1 预分频寄存器 */
#define REG_GTIM1_ARR			(*(volatile uint32_t *)(GTIMER1_BASE_ADDR + 0x20))	/* Timer1 自动重载寄存器 */
#define REG_GTIM1_CCR			(*(volatile uint32_t *)(GTIMER1_BASE_ADDR + 0x24))	/* Timer1 捕捉/比较寄存器 */
#define REG_GTIM1_CARS1			(*(volatile uint32_t *)(GTIMER1_BASE_ADDR + 0x28))	/* Timer1 捕捉/比较寄存器 */ 
	
/*----------------------------- GTIMER2 ------------------------------------------------*/
#define GTIMER2_BASE_ADDR		0x40003800
#define REG_GTIM2_CR			(*(volatile uint32_t *)(GTIMER2_BASE_ADDR + 0x00))	/* Timer2 控制寄存器 */	
#define REG_GTIM2_IER			(*(volatile uint32_t *)(GTIMER2_BASE_ADDR + 0x04))	/* Timer2 中断使能寄存器 */
#define REG_GTIM2_SR			(*(volatile uint32_t *)(GTIMER2_BASE_ADDR + 0x08))	/* Timer2 状态寄存器 */
#define REG_GTIM2_EGR			(*(volatile uint32_t *)(GTIMER2_BASE_ADDR + 0x0C))	/* Timer2 事件产生寄存器 */
#define REG_GTIM2_CCMR			(*(volatile uint32_t *)(GTIMER2_BASE_ADDR + 0x10))	/* Timer2 捕捉/比较寄存器 */
#define REG_GTIM2_CCER			(*(volatile uint32_t *)(GTIMER2_BASE_ADDR + 0x14))	/* Timer2 捕捉/比较使能寄存器 */
#define REG_GTIM2_CNT			(*(volatile uint32_t *)(GTIMER2_BASE_ADDR + 0x18))	/* Timer2 计数器寄存器 */
#define REG_GTIM2_PSC			(*(volatile uint32_t *)(GTIMER2_BASE_ADDR + 0x1C))	/* Timer2 预分频寄存器 */
#define REG_GTIM2_ARR			(*(volatile uint32_t *)(GTIMER2_BASE_ADDR + 0x20))	/* Timer2 自动重载寄存器 */
#define REG_GTIM2_CCR			(*(volatile uint32_t *)(GTIMER2_BASE_ADDR + 0x24))	/* Timer2 捕捉/比较寄存器 */
#define REG_GTIM2_CARS1			(*(volatile uint32_t *)(GTIMER2_BASE_ADDR + 0x28))	/* Timer2 捕捉/比较寄存器 */ 
	
/*------------------------------ WWDT ------------------------------------------------*/
#define WWDT_BASE_ADDR			0x40003C00
#define REG_WWDT_CON			(*(volatile uint32_t *)(WWDT_BASE_ADDR + 0x00))		/* WWDT控制寄存器 */
#define REG_WWDT_CFG			(*(volatile uint32_t *)(WWDT_BASE_ADDR + 0x04))		/* WWDT配置寄存器 */
#define REG_WWDT_CNT			(*(volatile uint32_t *)(WWDT_BASE_ADDR + 0x08))		/* WWDT计数寄存器 */
#define REG_WWDT_IE				(*(volatile uint32_t *)(WWDT_BASE_ADDR + 0x0C))		/* WWDT中断使能寄存器 */
#define REG_WWDT_IF				(*(volatile uint32_t *)(WWDT_BASE_ADDR + 0x10))		/* WWDT中断标志寄存器 */
	
/*------------------------------ GPIO --------------------------------------------------*/
#define GPIOA					0
#define GPIOB					1
#define GPIOC					2
#define GPIOD					3
#define GPIOE					4
#define GPIO_BASE_ADDR(x)		(0x40004000 + 0x0400 * (x))
#define REG_GPIO_DIR(x)			(*(volatile uint32_t *)(GPIO_BASE_ADDR(x) + 0x00))	/* GPIO 数据方向寄存器 */
#define REG_GPIO_SET(x)			(*(volatile uint32_t *)(GPIO_BASE_ADDR(x) + 0x08))	/* GPIO 输出置位寄存器 */
#define REG_GPIO_CLR(x)			(*(volatile uint32_t *)(GPIO_BASE_ADDR(x) + 0x0C))	/* GPIO 输出清零寄存器 */
#define REG_GPIO_ODATA(x)		(*(volatile uint32_t *)(GPIO_BASE_ADDR(x) + 0x10))	/* GPIO 输出引脚映射寄存器 */
#define REG_GPIO_IDATA(x)		(*(volatile uint32_t *)(GPIO_BASE_ADDR(x) + 0x14))	/* GPIO 输入引脚映射寄存器 */
#define REG_GPIO_IEN(x)			(*(volatile uint32_t *)(GPIO_BASE_ADDR(x) + 0x18))	/* GPIO 中断使能寄存器 */
#define REG_GPIO_IS(x)			(*(volatile uint32_t *)(GPIO_BASE_ADDR(x) + 0x1C))	/* GPIO 中断触发模式寄存器 */
#define REG_GPIO_IBE(x)			(*(volatile uint32_t *)(GPIO_BASE_ADDR(x) + 0x20))	/* GPIO 中断触发模式寄存器 */
#define REG_GPIO_IEV(x)			(*(volatile uint32_t *)(GPIO_BASE_ADDR(x) + 0x24))	/* GPIO 中断触发模式寄存器 */
#define REG_GPIO_IC(x)			(*(volatile uint32_t *)(GPIO_BASE_ADDR(x) + 0x28))	/* GPIO 中断状态清除寄存器 */
#define REG_GPIO_RIS(x)			(*(volatile uint32_t *)(GPIO_BASE_ADDR(x) + 0x2C))	/* GPIO 原始中断状态寄存器 */
#define REG_GPIO_MIS(x)			(*(volatile uint32_t *)(GPIO_BASE_ADDR(x) + 0x30))	/* GPIO 屏蔽后中断状态寄存器 */

/*------------------------------ I2C ---------------------------------------------------*/
#define I2C_BASE_ADDR			0x40005400
#define REG_I2C_CR              (*(volatile uint32_t *)(I2C_BASE_ADDR + 0x00))		/* I2C 配置寄存器 */
#define REG_I2C_CLR             (*(volatile uint32_t *)(I2C_BASE_ADDR + 0x04))		/* I2C 配置清除寄存器 */
#define REG_I2C_STAT            (*(volatile uint32_t *)(I2C_BASE_ADDR + 0x08))		/* I2C 状态寄存器 */
#define REG_I2C_DATA            (*(volatile uint32_t *)(I2C_BASE_ADDR + 0x0C))		/* I2C 数据寄存器 */
#define REG_I2C_CCR             (*(volatile uint32_t *)(I2C_BASE_ADDR + 0x10))		/* I2C 波特率配置寄存器 */
#define REG_I2C_SAD0            (*(volatile uint32_t *)(I2C_BASE_ADDR + 0x14))		/* I2C SLAVE地址寄存器0 */
#define REG_I2C_SADM0           (*(volatile uint32_t *)(I2C_BASE_ADDR + 0x18))		/* I2C SLAVE地址屏蔽寄存器0 */
#define REG_I2C_XSAD0           (*(volatile uint32_t *)(I2C_BASE_ADDR + 0x1C))		/* I2C SLAVE 扩展地址寄存器 */
#define REG_I2C_XSADM0          (*(volatile uint32_t *)(I2C_BASE_ADDR + 0x20))		/* I2C SLAVE 扩展地址屏蔽寄存器 */
#define REG_I2C_SRST            (*(volatile uint32_t *)(I2C_BASE_ADDR + 0x24))		/* I2C 复位寄存器 */
#define REG_I2C_SAD1            (*(volatile uint32_t *)(I2C_BASE_ADDR + 0x28))		/* I2C SLAVE地址寄存器1 */
#define REG_I2C_SADM1           (*(volatile uint32_t *)(I2C_BASE_ADDR + 0x2C))		/* I2C SLAVE地址屏蔽寄存器1 */
#define REG_I2C_SAD2            (*(volatile uint32_t *)(I2C_BASE_ADDR + 0x30))		/* I2C SLAVE地址寄存器2 */
#define REG_I2C_SADM2           (*(volatile uint32_t *)(I2C_BASE_ADDR + 0x34))		/* I2C SLAVE地址屏蔽寄存器2 */
#define REG_I2C_SAD3            (*(volatile uint32_t *)(I2C_BASE_ADDR + 0x38))		/* I2C SLAVE地址寄存器3 */
#define REG_I2C_SADM3           (*(volatile uint32_t *)(I2C_BASE_ADDR + 0x3C))		/* I2C SLAVE地址屏蔽寄存器3 */
	
/*----------------------------- SPI1 --------------------------------------------------*/
#define SPI1_BASE_ADDR			0x40005800
#define REG_SPI1_SPICR          (*(volatile uint32_t *)(SPI1_BASE_ADDR + 0x00))		/* SPI1 配置寄存器 */
#define REG_SPI1_SPICS0         (*(volatile uint32_t *)(SPI1_BASE_ADDR + 0x04))		/* SPI1 主模式控制寄存器0 */
#define REG_SPI1_SPICS1         (*(volatile uint32_t *)(SPI1_BASE_ADDR + 0x08))		/* SPI1 主模式控制寄存器1 */
#define REG_SPI1_SPIOPCR        (*(volatile uint32_t *)(SPI1_BASE_ADDR + 0x14))		/* SPI1 过程控制寄存器 */
#define REG_SPI1_SPIIE          (*(volatile uint32_t *)(SPI1_BASE_ADDR + 0x18))		/* SPI1 中断控制寄存器 */
#define REG_SPI1_SPIIF          (*(volatile uint32_t *)(SPI1_BASE_ADDR + 0x1c))		/* SPI1 中断标志寄存器 */
#define REG_SPI1_SPITXBUF       (*(volatile uint32_t *)(SPI1_BASE_ADDR + 0x20))		/* SPI1 接收缓存寄存器 */
#define REG_SPI1_SPIRXBUF       (*(volatile uint32_t *)(SPI1_BASE_ADDR + 0x24))		/* SPI1 接收缓存寄存器 */
#define REG_SPI1_DMA_SPIRX_LEV  (*(volatile uint32_t *)(SPI1_BASE_ADDR + 0x28))		/* SPI1 DMA接收设置寄存器 */
#define REG_SPI1_DMA_SPITX_LEV  (*(volatile uint32_t *)(SPI1_BASE_ADDR + 0x2C))		/* SPI1 DMA发送设置寄存器 */

/*----------------------------- CAN ---------------------------------------------------*/
#define CAN_BASE_ADDR			0x40005C00 

#define REG_CAN_MR				(*(volatile uint32_t *)(CAN_BASE_ADDR + 0x00))		/* 模式寄存器*/
#define REG_CAN_CMR				(*(volatile uint32_t *)(CAN_BASE_ADDR + 0x04))		/* 指令寄存器*/
#define REG_CAN_SR				(*(volatile uint32_t *)(CAN_BASE_ADDR + 0x08))		/* 控制寄存器*/
#define REG_CAN_ISR				(*(volatile uint32_t *)(CAN_BASE_ADDR + 0x0C))		/* 中断状态寄存器*/
#define REG_CAN_IMR				(*(volatile uint32_t *)(CAN_BASE_ADDR + 0x10))		/* 中断使能寄存器*/
#define REG_CAN_RMC				(*(volatile uint32_t *)(CAN_BASE_ADDR + 0x14))		/* 接收FIFO数据个数寄存器*/
#define REG_CAN_BTR0			(*(volatile uint32_t *)(CAN_BASE_ADDR + 0x18))		/* 总线时序寄存器0*/
#define REG_CAN_BTR1			(*(volatile uint32_t *)(CAN_BASE_ADDR + 0x1C))		/* 总线时序寄存器1*/
#define REG_CAN_TXBUF			(*(volatile uint32_t *)(CAN_BASE_ADDR + 0x20))		/* 发送缓存寄存器*/
#define REG_CAN_RXBUF			(*(volatile uint32_t *)(CAN_BASE_ADDR + 0x24))		/* 接收缓存寄存器*/
#define REG_CAN_ACR				(*(volatile uint32_t *)(CAN_BASE_ADDR + 0x28))		/* 接收过滤匹配寄存器*/
#define REG_CAN_AMR				(*(volatile uint32_t *)(CAN_BASE_ADDR + 0x2C))		/* 接收过滤屏蔽寄存器*/
#define REG_CAN_ECC				(*(volatile uint32_t *)(CAN_BASE_ADDR + 0x30))		/* 错误码捕捉寄存器*/
#define REG_CAN_RXERR			(*(volatile uint32_t *)(CAN_BASE_ADDR + 0x34))		/* 接收错误计数寄存器*/
#define REG_CAN_TXERR			(*(volatile uint32_t *)(CAN_BASE_ADDR + 0x38))		/* 发送错误寄存器*/
#define REG_CAN_ALC				(*(volatile uint32_t *)(CAN_BASE_ADDR + 0x3C))		/* 仲裁丢失捕获寄存器*/
#define REG_CAN_RXADDR			(*(volatile uint32_t *)(CAN_BASE_ADDR + 0x40))		/* 接收缓存基地址设置寄存器*/


/*----------------------------- DMA ---------------------------------------------------*/
#define DMA_BASE_ADDR			0x40020000 
	
#define REG_DMA_SRCADDRC0		(*(volatile uint32_t *)(DMA_BASE_ADDR + 0x00))		/* 通道0源地址寄存器 */
#define REG_DMA_DSTADDRC0		(*(volatile uint32_t *)(DMA_BASE_ADDR + 0x04))		/* 通道0目的地址寄存器 */
#define REG_DMA_CHCTRLC0		(*(volatile uint32_t *)(DMA_BASE_ADDR + 0x08))		/* 通道0控制信息寄存器 */
#define REG_DMA_CHSTSC0			(*(volatile uint32_t *)(DMA_BASE_ADDR + 0x0C))		/* 通道0传送状态寄存器 */
#define REG_DMA_SRCADDRC1		(*(volatile uint32_t *)(DMA_BASE_ADDR + 0x10))		/* 通道1源地址寄存器 */
#define REG_DMA_DSTADDRC1		(*(volatile uint32_t *)(DMA_BASE_ADDR + 0x14))		/* 通道1目的地址寄存器 */
#define REG_DMA_CHCTRLC1		(*(volatile uint32_t *)(DMA_BASE_ADDR + 0x18))		/* 通道1控制信息寄存器 */
#define REG_DMA_CHSTSC1			(*(volatile uint32_t *)(DMA_BASE_ADDR + 0x1C))		/* 通道1传送状态寄存器 */
#define REG_DMA_SRCADDRC2		(*(volatile uint32_t *)(DMA_BASE_ADDR + 0x20))		/* 通道2源地址寄存器 */
#define REG_DMA_DSTADDRC2		(*(volatile uint32_t *)(DMA_BASE_ADDR + 0x24))		/* 通道2目的地址寄存器 */
#define REG_DMA_CHCTRLC2		(*(volatile uint32_t *)(DMA_BASE_ADDR + 0x28))		/* 通道2控制信息寄存器 */
#define REG_DMA_CHSTSC2			(*(volatile uint32_t *)(DMA_BASE_ADDR + 0x2C))		/* 通道2传送状态寄存器 */
#define REG_DMA_SRCADDRC3		(*(volatile uint32_t *)(DMA_BASE_ADDR + 0x30))		/* 通道3源地址寄存器 */
#define REG_DMA_DSTADDRC3		(*(volatile uint32_t *)(DMA_BASE_ADDR + 0x34))		/* 通道3目的地址寄存器 */
#define REG_DMA_CHCTRLC3		(*(volatile uint32_t *)(DMA_BASE_ADDR + 0x38))		/* 通道3控制信息寄存器 */
#define REG_DMA_CHSTSC3			(*(volatile uint32_t *)(DMA_BASE_ADDR + 0x3C))		/* 通道3传送状态寄存器 */
#define REG_DMA_EN				(*(volatile uint32_t *)(DMA_BASE_ADDR + 0x40))		/* DMA控制器使能 */
#define REG_DMA_SOFTRESET		(*(volatile uint32_t *)(DMA_BASE_ADDR + 0x44))		/* DMA软复位 */
#define REG_DMA_INTSTATUS		(*(volatile uint32_t *)(DMA_BASE_ADDR + 0x48))		/* DMA中断指示寄存器 */	
#define REG_DMA_INTMASK			(*(volatile uint32_t *)(DMA_BASE_ADDR + 0x4C))		/* DMA中断屏蔽寄存器 */
#define REG_DMA_BASICINFM		(*(volatile uint32_t *)(DMA_BASE_ADDR + 0x50))		/* DMA基本信息 */
#define REG_DMA_PERREQ			(*(volatile uint32_t *)(DMA_BASE_ADDR + 0x54))		/* DMA外设请求信息 */
	
	
/*----------------------------- CACHE ---------------------------------------------------*/
#define CACHE_BASE_ADDR			0x20004400
#define REG_CACHE_CACR			(*(volatile uint32_t *)(CACHE_BASE_ADDR))

/*----------------------------- System Tick -------------------------------------------*/
#define SYSTICK_BASE_ADDR		0xE000E010
#define REG_SYSTICK_CSR         (*(volatile uint32_t *)(SYSTICK_BASE_ADDR + 0x00))	/* SysTick控制和状态寄存器 */
#define REG_SYSTICK_RVR         (*(volatile uint32_t *)(SYSTICK_BASE_ADDR + 0x04))	/* SysTick重载值寄存器 */
#define REG_SYSTICK_CVR         (*(volatile uint32_t *)(SYSTICK_BASE_ADDR + 0x08))	/* SysTick当前值寄存器 */

#endif
